Flexflow: A flexible dataflow accelerator architecture for convolutional neural networks W Lu, G Yan, J Li, S Gong, Y Han, X Li 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 165 | 2017 |
Agileregulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture G Yan, Y Li, Y Han, X Li, M Guo, X Liang IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 67 | 2012 |
Smartcap: User experience-oriented power adaptation for smartphone's application processor X Li, G Yan, Y Han, X Li 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 57-60, 2013 | 36 | 2013 |
Smartshuttle: Optimizing off-chip memory accesses for deep learning accelerators J Li, G Yan, W Lu, S Jiang, S Gong, J Wu, X Li 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 343-348, 2018 | 28 | 2018 |
A unified online fault detection scheme via checking of stability violation G Yan, Y Han, X Li 2009 Design, Automation & Test in Europe Conference & Exhibition, 496-501, 2009 | 25 | 2009 |
A Unified Online Fault Detection Scheme via Checking of Stability Violation G Yan, Y Han, X Li Proc. Conf. Des., Autom. Test Euro.(DATE), 2009 | 25 | 2009 |
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors G Yan, X Liang, Y Han, X Li Proceedings of the 37th annual international symposium on Computer …, 2010 | 24 | 2010 |
AxTrain: Hardware-oriented neural network training for approximate inference X He, L Ke, W Lu, G Yan, X Zhang Proceedings of the International Symposium on Low Power Electronics and …, 2018 | 21 | 2018 |
An analytical framework for estimating scale-out and scale-up power efficiency of heterogeneous manycores J Ma, G Yan, Y Han, X Li IEEE Transactions on Computers 65 (2), 367-381, 2015 | 20 | 2015 |
SVFD: A versatile online fault detection scheme via checking of stability violation G Yan, Y Han, X Li IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010 | 20 | 2010 |
ReviveNet: A self-adaptive architecture for improving lifetime reliability via localized timing adaptation G Yan, Y Han, X Li IEEE Transactions on Computers 60 (9), 1219-1232, 2011 | 16 | 2011 |
M-IVC: Using multiple input vectors to minimize aging-induced delay S Jin, Y Han, L Zhang, H Li, X Li, G Yan 2009 Asian Test Symposium, 437-442, 2009 | 12 | 2009 |
ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation H Lu, G Yan, Y Han, Y Wang, X Li The 20th Asia and South Pacific Design Automation Conference, 142-147, 2015 | 11 | 2015 |
Superrange: wide operational range power delivery design for both stv and ntv computing X He, G Yan, Y Han, X Li 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 11 | 2014 |
RISO: Relaxed network-on-chip isolation for cloud processors H Lu, G Yan, Y Han, B Fu, X Li Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 11 | 2013 |
SqueezeFlow: A sparse CNN accelerator exploiting concise convolution rules J Li, S Jiang, S Gong, J Wu, J Yan, G Yan, X Li IEEE Transactions on Computers 68 (11), 1663-1677, 2019 | 10 | 2019 |
ACR: Enabling computation reuse for approximate computing X He, G Yan, Y Han, X Li 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 643-648, 2016 | 10 | 2016 |
CoreRank: redeeming “Sick Silicon” by dynamically quantifying core-level healthy condition G Yan, F Sun, H Li, X Li IEEE Transactions on Computers 65 (3), 716-729, 2015 | 10 | 2015 |
Orchestrator: A low-cost solution to reduce voltage emergencies for multi-threaded applications X Hu, G Yan, Y Hu, X Li 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 208-213, 2013 | 10 | 2013 |
Joint design of training and hardware towards efficient and accuracy-scalable neural network inference X He, W Lu, G Yan, X Zhang IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4 …, 2018 | 9* | 2018 |