| All-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters S Chen, L Wang, H Zhang, R Murugesu, D Dunwell, AC Carusone IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017 | 67 | 2017 |
| Modeling oscillator injection locking using the phase domain response D Dunwell, AC Carusone IEEE Transactions on Circuits and Systems I: Regular Papers 60 (11), 2823-2833, 2013 | 65 | 2013 |
| A 5.6 Gb/s 2.4 mW/Gb/s bidirectional link with 8ns power-on J Zerbe, B Daly, W Dettloff, T Stone, W Stonecypher, P Venkatesan, ... 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 82-83, 2011 | 39 | 2011 |
| 30.5 A 1.41 pJ/b 56Gb/s PAM-4 wireline receiver employing enhanced pattern utilization CDR and genetic adaptation algorithms in 7nm CMOS S Shahramian, B Dehlaghi, J Liang, R Bespalko, D Dunwell, J Bailey, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 482-484, 2019 | 28 | 2019 |
| Integrated circuit having a multiplying injection-locked oscillator JL Zerbe, BW Daly, DT Dunwell, AC Carusone, JC Eble III US Patent 9,154,145, 2015 | 26 | 2015 |
| Accumulation-mode MOS varactors for RF CMOS low-noise amplifiers D Dunwell, B Frank 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems …, 2007 | 19 | 2007 |
| Computer design of super-orthogonal space-time trellis codes M Bale, B Laska, D Dunwell, F Chan, H Jafarkhani IEEE transactions on wireless communications 6 (2), 463-467, 2007 | 18 | 2007 |
| A 2.3–4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on D Dunwell, AC Carusone, J Zerbe, B Leibowitz, B Daly, J Eble Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 14 | 2012 |
| A 1.41-pJ/b 56-Gb/s PAM-4 receiver using enhanced transition utilization CDR and genetic adaptation algorithms in 7-nm CMOS B Dehlaghi, S Shahramian, J Liang, R Bespalko, D Dunwell, J Bailey, ... IEEE Solid-State Circuits Letters 2 (11), 248-251, 2019 | 13 | 2019 |
| Integrated circuit having a multiplying injection-locked oscillator JL Zerbe, BW Daly, DT Dunwell, AC Carusone, JC Eble III US Patent 9,564,911, 2017 | 11 | 2017 |
| Integrated circuit having a multiplying injection-locked oscillator JL Zerbe, BW Daly, DT Dunwell, AC Carusone, JC Eble III US Patent 10,404,262, 2019 | 10 | 2019 |
| Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver D Dunwell, AC Carusone IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 9 | 2010 |
| 24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18 μm CMOS D Dunwell, B Frank 2006 Canadian Conference on Electrical and Computer Engineering, 1918-1921, 2006 | 6 | 2006 |
| Frequency/phase-shift-keying for back-channel serdes communication D Tonietto, DT Dunwell, AC Carusone US Patent 10,153,917, 2018 | 4 | 2018 |
| Computer design of super-orthogonal space-time trellis codes B Laska, D Dunwell, F Chan, H Jafarkhani Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat …, 2004 | 4 | 2004 |
| A 15-Gb/s Preamplifier with 10-dB Gain Control and 8-mV Sensitivity in 65-nm CMOS D Dunwell, AC Carusone Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 3 | 2010 |
| Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation YF Zhang, J Liang, S Shahramian, B Dehlaghi, R Bespalko, M O’Farrel, ... IEEE Solid-State Circuits Letters 3, 25-28, 2019 | 1 | 2019 |
| A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC M Bichan, D Dunwell, Q Wang, AC Carusone 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1320-1323, 2014 | 1 | 2014 |
| IEEE SSCS Toronto Chapter Holds First In-Person Wireline Workshop [Chapters] D Dunwell IEEE Solid-State Circuits Magazine 15 (2), 106-107, 2023 | | 2023 |
| Channel characterization using jitter measurements D Dunwell, A Gupta, AC Carusone 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2666-2669, 2013 | | 2013 |
