| A structured test re-use methodology for core-based system chips P Varma, S Bhatia Test Conference, 1998. Proceedings., International, 294-302, 1998 | 344 | 1998 |
| Genesis: A behavioral synthesis system for hierarchical testability S Bhatia, NK Jha Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 272-276, 1994 | 118 | 1994 |
| A unifying methodology for intellectual property and custom logic testing S Bhatia, T Gheewala, P Varma Proceedings International Test Conference 1996. Test and Design Validity …, 1996 | 67 | 1996 |
| Method and mechanism for implementing electronic designs having power information specifications background Q Wang, A Gupta, P Chen, C Chu, M Pandey, HC Tsai, S Bhatia, Y Chen, ... US Patent 7,739,629, 2010 | 55 | 2010 |
| Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches S Bhatia, NK Jha Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994 | 50 | 1994 |
| Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits S Bhatia, NK Jha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (4), 608-619, 1998 | 46 | 1998 |
| Synthesis of sequential circuits for easy testability through performance-oriented parallel partial scan S Bhatia, NK Jha Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 …, 1993 | 20 | 1993 |
| Method and system for clock skew independent scan register chains S Bhatia US Patent 7,613,969, 2009 | 19 | 2009 |
| Test compaction in a parallel access scan environment S Bhatia, P Varma Proceedings Sixth Asian Test Symposium (ATS'97), 300-305, 1997 | 17 | 1997 |
| Test compaction in a parallel access scan environment S Bhatia, P Varma Proceedings Sixth Asian Test Symposium (ATS'97), 300-305, 1997 | 17 | 1997 |
| A structured test re-use methodology for systems on silicon P Varma, S Bhatia IEEE TECS Workshop, 1997 | 14 | 1997 |
| Low power scan test for integrated circuits BL Keller, V Chickermane, S Bhatia US Patent 7,693,676, 2010 | 13 | 2010 |
| Test compaction by using linear-matrix driven scan chains S Bhatia Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003 | 13 | 2003 |
| IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers Y Li, M Shao, H Jiao, A Cron, S Bhatia, EJ Marinissen 2018 IEEE 23rd European Test Symposium (ETS), 1-6, 2018 | 11 | 2018 |
| Scan register and methods of using the same S Bhatia, O Roig US Patent 7,457,998, 2008 | 11 | 2008 |
| Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability S Bhatia, NJ Jha IEEE transactions on computer-aided design of integrated circuits and …, 1996 | 11 | 1996 |
| Low power compression architecture S Bhatia 2010 28th VLSI Test Symposium (VTS), 183-187, 2010 | 8 | 2010 |
| Method and mechanism for implementing electronic designs having power information specifications background Q Wang, A Gupta, P Chen, C Chu, M Pandey, HC Tsai, S Bhatia, Y Chen, ... US Patent 8,516,422, 2013 | 7 | 2013 |
| Test compaction using linear-matrix driven scan chains S Bhatia US Patent 7,925,941, 2011 | 7 | 2011 |
| Dual scan chain design method and apparatus S Bhatia US Patent 7,657,809, 2010 | 7 | 2010 |
