Anindya Sundar Dhar
Anindya Sundar Dhar
Professor, Dept. of Electronics and Electrical Communication Engineering, Indian Institute of
Verified email at ece.iitkgp.ernet.in
Title
Cited by
Cited by
Year
CORDIC architectures: a survey
B Lakshmi, AS Dhar
VLSI design 2010, 2010
902010
FPGA realization of a CORDIC based FFT processor for biomedical signal processing
A Banerjee, AS Dhar, S Banerjee
Microprocessors and Microsystems 25 (3), 131-142, 2001
822001
An array architecture for fast computation of discrete Hartley transform
AS Dhar, S Banerjee
IEEE transactions on circuits and systems 38 (9), 1095-1098, 1991
671991
A VLSI array architecture for realization of DFT, DHT, DCT and DST
K Maharatna, AS Dhar, S Banerjee
Signal Processing 81 (9), 1813-1822, 2001
612001
CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis
KC Ray, AS Dhar
IEE Proceedings-Circuits, Devices and Systems 153 (6), 539-544, 2006
352006
Architectural design and FPGA implementation of radix-4 CORDIC processor
K Bhattacharyya, R Biswas, AS Dhar, S Banerjee
Microprocessors and Microsystems 34 (2-4), 96-101, 2010
272010
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC
M Chakraborty, AS Dhar, MH Lee
IEEE Transactions on Circuits and Systems II: Express Briefs 52 (9), 530-534, 2005
252005
CORDIC unit
K Maharatna, E Grass, B Swapna, DA Sundar
US Patent 7,606,852, 2009
182009
Real-time fault-tolerance with hot-standby topology for conditional sum adder
A Mukherjee, AS Dhar
Microelectronics Reliability 55 (3-4), 704-712, 2015
172015
VLSI architecture for parallel radix-4 CORDIC
B Lakshmi, AS Dhar
Microprocessors and Microsystems 37 (1), 79-86, 2013
172013
VLSI architecture for low latency radix-4 CORDIC
B Lakshmi, AS Dhar
Computers & Electrical Engineering 37 (6), 1032-1042, 2011
172011
FPGA implementation of discrete fractional Fourier transform
M Prasad, KC Ray, AS Dhar
2010 International Conference on Signal Processing and Communications (SPCOM …, 2010
152010
Multiplierless array architecture for computing discrete cosine transform
MC Mandal, AS Dhar, S Banerjee
Computers & electrical engineering 21 (1), 13-19, 1995
131995
Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs
A Palchaudhuri, AS Dhar
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
122016
Sampled analog architecture for DCT and DST
AK Mal, A Basu, AS Dhar
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
122004
Digital controlled analog architecture for DCT and DST using capacitor switching
A Basu, AK Mal, AS Dhar
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
112004
VLSI architecture for multi-resolution three step search algorithm
M Sarma, D Samanta, AS Dhar
ASIC, 2003. Proceedings. 5th International Conference on 2, 918-921, 2003
112003
Low-delay parallel architecture for fractal image compression
M Panigrahy, I Chakrabarti, AS Dhar
Circuits, Systems, and Signal Processing 35 (3), 897-917, 2016
102016
Pipelined VLSI architecture using CORDIC for transform domain equalizer
A Banerjee, AS Dhar
Journal of Signal Processing Systems 70 (1), 39-48, 2013
102013
High speed architectural implementation of CORDIC algorithm
B Lakshmi, AS Dhar
TENCON 2008-2008 IEEE Region 10 Conference, 1-5, 2008
102008
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