Li Jiang
Title
Cited by
Cited by
Year
Test architecture design and optimization for three-dimensional SoCs
L Jiang, L Huang, Q Xu
2009 Design, Automation & Test in Europe Conference & Exhibition, 220-225, 2009
1122009
On effective TSV repair for 3D-stacked ICs
L Jiang, Q Xu, B Eklow
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 793-798, 2012
1012012
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
L Jiang, Q Xu, K Chakrabarty, TM Mak
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
892009
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar
L Chen, J Li, Y Chen, Q Deng, J Shen, X Liang, L Jiang
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 19-24, 2017
782017
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
L Jiang, R Ye, Q Xu
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 230-234, 2010
712010
On effective through-silicon via repair for 3-D-stacked ICs
L Jiang, Q Xu, B Eklow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
542013
On effective and efficient in-field TSV repair for stacked 3D ICs
L Jiang, F Ye, Q Xu, K Chakrabarty, B Eklow
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
422013
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Q Xu, L Jiang, H Li, B Eklow
17th Asia and South Pacific Design Automation Conference, 731-737, 2012
362012
Modeling TSV open defects in 3D-stacked DRAM
L Jiang, Y Liu, L Duan, Y Xie, Q Xu
2010 IEEE International Test Conference, 1-9, 2010
352010
Integrated test-architecture optimization and thermal-aware test scheduling for 3-D SoCs under pre-bond test-pin-count constraint
L Jiang, Q Xu, K Chakrabarty, TM Mak
IEEE transactions on very large scale integration (VLSI) systems 20 (9 …, 2011
222011
ReCom: An efficient resistive accelerator for compressed deep neural networks
H Ji, L Song, L Jiang, HH Li, Y Chen
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 237-240, 2018
202018
Energy-efficient eDRAM-based on-chip storage architecture for GPGPUs
N Jing, L Jiang, T Zhang, C Li, F Fan, X Liang
IEEE Transactions on Computers 65 (1), 122-135, 2015
172015
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
N Jing, J Wang, F Fan, W Yu, L Jiang, C Li, X Liang
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
142016
On quality trade-off control for approximate computing using iterative training
C Xu, X Wu, W Yin, Q Xu, N Jing, X Liang, L Jiang
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
112017
AgentDiag: An agent-assisted diagnostic framework for board-level functional failures
Z Sun, L Jiang, Q Xu, Z Zhang, Z Wang, X Gu
2013 IEEE International Test Conference (ITC), 1-8, 2013
112013
Bank stealing for conflict mitigation in GPGPU register file
N Jing, S Chen, S Jiang, L Jiang, C Li, X Liang
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
102015
Fault-tolerant 3D-NoC architecture and design: recent advances and challenges
L Jiang, Q Xu
Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015
92015
System-level hardware failure prediction using deep learning
X Sun, K Chakrabarty, R Huang, Y Chen, B Zhao, H Cao, Y Han, X Liang, ...
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
82019
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing
H Ji, L Jiang, T Li, N Jing, J Ke, X Liang
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
62019
Incorporating selective victim cache into GPGPU for high‐performance computing
J Wang, F Fan, L Jiang, X Liang, N Jing
Concurrency and Computation: Practice and Experience 29 (24), e4104, 2017
62017
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