Ashish Goel
Ashish Goel
Purdue University, Broadcom Corporation
Verified email at broadcom.com
Title
Cited by
Cited by
Year
Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
J Li, P Ndai, A Goel, S Salahuddin, K Roy
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18 (12 …, 2010
1242010
Asymmetric Drain Spacer Extension (ADSE) FinFETs for low-power and robust SRAMs
A Goel, SK Gupta, K Roy
Electron Devices, IEEE Transactions on 58 (2), 296-308, 2011
1032011
Modeling and circuit synthesis for independently controlled double gate FinFET devices
A Datta, A Goel, RT Cakici, H Mahmoodi, D Lekshmanan, K Roy
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2007
982007
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
A Goel, S Bhunia, H Mahmoodi, K Roy
Design Automation, 2006. Asia and South Pacific Conference on, 6 pp., 2006
402006
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
J Li, P Ndai, A Goel, H Liu, K Roy
Proceedings of the 2009 Asia and South Pacific Design Automation Conference …, 2009
312009
A read-disturb-free, differential sensing 1R/1W port, 8T Bitcell array
JP Kulkarni, A Goel, P Ndai, K Roy
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 19 (9 …, 2011
292011
Data-dependant sense-amplifier flip-flop for low power applications
F Moradi, C Augustine, A Goel, G Karakonstantis, TV Cao, D Wisland, ...
Custom Integrated Circuits Conference (CICC), 2010 IEEE, 1-4, 2010
112010
A scalable circuit-architecture co-design to improve memory yield for high-performance processors
P Ndai, A Goel, K Roy
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18 (8 …, 2010
112010
Memory-based embedded digital ATE
D Lee, SP Park, A Goel, K Roy
VLSI Test Symposium (VTS), 2011 IEEE 29th, 266-271, 2011
102011
ISSCC 2010/SESSION 9/DIGITAL CIRCUITS & SENSORS/9.7
SSFRB Circuit
9*2010
Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM
A Goel, S Gupta, A Bansal, MH Chiang, K Roy
Device Research Conference, 2009. DRC 2009, 57-58, 2009
62009
REad/access-preferred (REAP) SRAM-architecture-aware bit cell design for improved yield and lower V MIN
A Goel, P Ndai, JP Kulkarni, K Roy
Custom Integrated Circuits Conference, 2009. CICC'09. IEEE, 503-506, 2009
22009
HBIST: An approach towards zero external test cost
M Bubna, K Roy, A Goel
VLSI Test Symposium (VTS), 2012 IEEE 30th, 13-18, 2012
12012
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost
A Goel, S Ghosh, M Meterelliyoz, J Parkhurst, K Roy
Test Symposium (ATS), 2011 20th Asian, 486-491, 2011
2011
Low-power, process and error tolerant circuit design for nanometer technologies
A Goel
2010
STT-RAM Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective
J Li, P Ndai, A Goel, S Salahuddin, K Roy
IEEE transactions on very large scale integration (VLSI) systems 18 (12), 0
The system can't perform the operation now. Try again later.
Articles 1–16