Takip et
Brian Cline
Brian Cline
Principal Research Engineer, ARM
arm.com üzerinde doğrulanmış e-posta adresine sahip
Alıntı yapanlar
Alıntı yapanlar
Exploring sub-20nm FinFET design with predictive technology models
S Sinha, G Yeric, V Chandra, B Cline, Y Cao
DAC Design Automation Conference 2012, 283-288, 2012
ASAP7: A 7-nm finFET predictive process design kit
LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ...
Microelectronics Journal 53, 105-115, 2016
Exploring variability and performance in a sub-200-mV processor
S Hanson, B Zhai, M Seok, B Cline, K Zhou, M Singhal, M Minuth, J Olson, ...
IEEE Journal of Solid-State Circuits 43 (4), 881-891, 2008
Analysis and modeling of CD variation for statistical static timing
B Cline, K Chopra, D Blaauw, Y Cao
2006 IEEE/ACM International Conference on Computer Aided Design, 60-66, 2006
Performance and variability optimization strategies in a sub-200mV, 3.5 pJ/inst, 11nW subthreshold processor
S Hanson, B Zhai, M Seok, B Cline, K Zhou, M Singhal, M Minuth, J Olson, ...
2007 IEEE Symposium on VLSI Circuits, 152-153, 2007
Correlated electron switch programmable fabric
L Shifren, G Yeric, S Sinha, B Cline, V Chandra
US Patent 10,056,143, 2018
Self-aligned double patterning aware pin access and standard cell layout co-optimization
X Xu, B Cline, G Yeric, B Yu, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization
X Xu, B Cline, G Yeric, B Yu, DZ Pan
ACM International Symposium on Physical Design, 2014
Computer implemented system and method for generating a layout of a cell defining a circuit component
P De Dood, MW Frederick, JC Wang, BDN Lee, BT Cline, X Xu, AW Chen, ...
US Patent 10,083,269, 2018
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools
K Chang, S Sinha, B Cline, R Southerland, M Doherty, G Yeric, SK Lim
Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016
Physical design and FinFETs
R Aitken, G Yeric, B Cline, S Sinha, L Shifren, I Iqbal, V Chandra
Proceedings of the 2014 on International symposium on physical design, 65-68, 2014
Design benchmarking to 7nm with FinFET predictive technology models
S Sinha, B Cline, G Yeric, V Chandra, Y Cao
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Stress aware layout optimization
V Joshi, B Cline, D Sylvester, D Blaauw, K Agarwal
Proceedings of the 2008 international symposium on Physical design, 168-174, 2008
Standard cell library design and optimization methodology for ASAP7 PDK
X Xu, N Shah, A Evans, S Sinha, B Cline, G Yeric
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 999 …, 2017
Predictive simulation and benchmarking of Si and Ge pMOS FinFETs for future CMOS technology
L Shifren, R Aitken, AR Brown, V Chandra, B Cheng, C Riddet, ...
IEEE Transactions on Electron Devices 61 (7), 2271-2277, 2014
Replacing copper interconnects with graphene at a 7-nm node
NC Wang, S Sinha, B Cline, CD English, G Yeric, E Pop
2017 IEEE International Interconnect Technology Conference (IITC), 1-3, 2017
Circuit and method for configurable impedance array
AJ Bhavnagarwala, V Chandra, BT Cline
US Patent 9,773,550, 2017
32-bit processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance
CS Lee, B Cline, S Sinha, G Yeric, HSP Wong
2016 IEEE International Electron Devices Meeting (IEDM), 28.3. 1-28.3. 4, 2016
Leakage power reduction using stress-enhanced layouts
V Joshi, B Cline, D Sylvester, D Blaauw, K Agarwal
2008 45th ACM/IEEE Design Automation Conference, 912-917, 2008
Power benefit study of monolithic 3D IC at the 7nm technology node
K Chang, K Acharya, S Sinha, B Cline, G Yeric, SK Lim
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
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Makaleler 1–20