Jaydeep P. Kulkarni
Jaydeep P. Kulkarni
Electrical and Computer Engineering, University of Texas at Austin
Verified email at austin.utexas.edu - Homepage
Title
Cited by
Cited by
Year
Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates
Q Cao, H Kim, N Pimparkar, JP Kulkarni, C Wang, M Shim, K Roy, ...
Nature 454 (7203), 495-500, 2008
11832008
A 160 mV robust Schmitt trigger based subthreshold SRAM
JP Kulkarni, K Kim, K Roy
IEEE Journal of Solid-State Circuits 42 (10), 2303-2313, 2007
4342007
Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design
JP Kulkarni, K Roy
IEEE transactions on very large scale integration (VLSI) systems 20 (2), 319-332, 2011
1392011
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
V Saripalli, S Datta, V Narayanan, JP Kulkarni
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 45-52, 2011
1002011
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
JP Kulkarni, K Kim, K Roy
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
862007
A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS
R Jain, BM Geuskens, ST Kim, MM Khellah, J Kulkarni, JW Tschanz, V De
IEEE Journal of Solid-State Circuits 49 (4), 917-927, 2014
852014
Communication device with active equalization and method therefor
JD McIntosh
US Patent 6,639,987, 2003
782003
Communication device with active equalization and method therefor
JD McIntosh
US Patent 6,639,987, 2003
782003
Process variation tolerant SRAM array for ultra low voltage applications
JP Kulkarni, K Kim, SP Park, K Roy
Proceedings of the 45th annual Design Automation Conference, 108-113, 2008
712008
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
A Raychowdhury, B Geuskens, J Kulkarni, J Tschanz, K Bowman, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 352-353, 2010
702010
Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled fully integrated voltage regulator
ST Kim, YC Shih, K Mazumdar, R Jain, JF Ryan, C Tokunaga, ...
IEEE Journal of Solid-State Circuits 51 (1), 18-30, 2015
382015
Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating
M Cho, ST Kim, C Tokunaga, C Augustine, JP Kulkarni, K Ravichandran, ...
IEEE Journal of Solid-State Circuits 52 (1), 50-63, 2016
372016
Capacitive-coupling wordline boosting with self-induced VCCcollapse for write VMINreduction in 22-nm 8T SRAM
J Kulkarni, B Geuskens, T Karnik, M Khellah, J Tschanz, V De
2012 IEEE International Solid-State Circuits Conference, 234-236, 2012
362012
Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks
JP Kulkarni, BM Geuskens, J Tschanz, VK De, MM Khellah
US Patent 9,299,395, 2016
342016
A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS
R Jain, B Geuskens, M Khellah, S Kim, J Kulkarni, J Tschanz, V De
2013 Symposium on VLSI Circuits, C174-C175, 2013
312013
Improving multi-core performance using mixed-cell cache architecture
SM Khan, AR Alameldeen, C Wilkerson, J Kulkarni, DA Jimenez
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
302013
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep
C Tokunaga, JF Ryan, C Augustine, JP Kulkarni, YC Shih, ST Kim, R Jain, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
292014
Process-tolerant ultralow voltage digital subthreshold design
K Roy, JP Kulkarni, ME Hwang
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF …, 2008
292008
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation
ST Kim, YC Shih, K Mazumdar, R Jain, JF Ryan, C Tokunaga, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
282015
A read-disturb-free, differential sensing 1R/1W port, 8T bitcell array
JP Kulkarni, A Goel, P Ndai, K Roy
IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010
282010
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