| Multithreaded data processing method with long latency subinstructions ME Hwang US Patent 6,216,220, 2001 | 104 | 2001 |
| A 85mV 40nW process-tolerant subthreshold 8× 8 FIR filter in 130nm technology ME Hwang, A Raychowdhury, K Kim, K Roy 2007 IEEE Symposium on VLSI Circuits, 154-155, 2007 | 74 | 2007 |
| Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation ME Hwang, SO Jung, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 56 (7), 1428-1441, 2008 | 43 | 2008 |
| A 135mV 0.13 μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology ME Hwang, K Roy 2008 IEEE Custom Integrated Circuits Conference, 419-422, 2008 | 34 | 2008 |
| Energy-recovery techniques to reduce on-chip power density in molecular nanotechnologies ME Hwang, A Raychowdhury, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 52 (8), 1580-1589, 2005 | 34 | 2005 |
| ABRM: Adaptive -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling ME Hwang, K Roy IEEE transactions on very large scale integration (VLSI) systems 18 (2), 281-290, 2009 | 33 | 2009 |
| Process-tolerant ultralow voltage digital subthreshold design K Roy, JP Kulkarni, ME Hwang 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF …, 2008 | 30 | 2008 |
| Supply-voltage scaling close to the fundamental limit under process variations in nanometer technologies ME Hwang IEEE transactions on electron devices 58 (8), 2808-2813, 2011 | 20 | 2011 |
| Method and apparatus of estimating circuit delay ME Hwang, SO Jung US Patent 7,721,236, 2010 | 19 | 2010 |
| Exploration of the method of the Interconnect Effort in Nano-Technologies ME Hwang, SO Jung US Patent App. 11/532,878, 2007 | 11 | 2007 |
| Process Tolerant ß-ratio Modulation for Ultra-Dynamic Voltage Scaling ME Hwang, T Cakici, K Roy 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 9 | 2007 |
| Storage device, computing system including the storage device, and method of operating the storage device ME Hwang, KJ Jung, TH Lee, KH Choi, SK Jeong US Patent 10,048,899, 2018 | 5 | 2018 |
| A 85 mV 40 nW process tolerant 8× 8 FIR filter with ultra-dynamic voltage scaling ME Hwang, A Raychowdhury, K Kim, K Roy Proc. of IEEE VLSI Circuit Symposium, June 2007, 154-155, 2007 | 5 | 2007 |
| A 0.94 μW 611 KHz in-situ logic operation in embedded DRAM memory arrays in 90 nm CMOS ME Hwang, S Kwon Electronics 8 (8), 865, 2019 | 3 | 2019 |
| Data storage device that divides and processes a command and data processing system including the same GJ Jeong, TH Lee, SK Jeong, KH Choi, ME Hwang US Patent 10,303,366, 2019 | 3 | 2019 |
| Low power latch using multi-threshold voltage or stack-structured transistor ME Hwang US Patent App. 13/313,807, 2012 | 2 | 2012 |
| DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling. ME Hwang, S Kwon Journal of Electrical & Computer Engineering, 2016 | 1 | 2016 |
| Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates ME Hwang, SO Jung, K Roy Proceedings of the 2007 international symposium on Low power electronics and …, 2007 | 1 | 2007 |
| Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies ME Hwang, A Raychowdhury, K Roy 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 3, III-709, 2004 | 1 | 2004 |
| Storage device, computing system including the storage device, and method of operating the storage device ME Hwang, KJ Jung, TH Lee, KH Choi, SK Jeong US Patent App. 16/029,007, 2018 | | 2018 |
