| Significance of nanotechnology in construction engineering AK Rana, SB Rana, A Kumari, V Kiran International Journal of Recent Trends in Engineering 1 (4), 46, 2009 | 122 | 2009 |
| Physical scaling limits of FinFET structure: A simulation study G Saini, AK Rana International Journal of VLSI design & communication Systems (VLSICS) 2 (1 …, 2011 | 50 | 2011 |
| Impact of various parameters on the performance of free space optics communication system N Kumar, AK Rana Optik 124 (22), 5774-5776, 2013 | 45 | 2013 |
| Impact of channel doping on dgmosfet parameters in nano regime-tcad simulation VK Yadav, AK Rana Int. J. Comput. Appl 37 (11), 36-41, 2012 | 37 | 2012 |
| Adiabatic technique for energy efficient logic circuits design RK Yadav, AK Rana, S Chauhan, D Ranka, K Yadav 2011 International Conference on Emerging Trends in Electrical and Computer …, 2011 | 33 | 2011 |
| New low-power techniques: leakage feedback with stack & sleep stack with keeper PK Pal, RS Rathore, AK Rana, G Saini 2010 International Conference on Computer and Communication Technology …, 2010 | 32 | 2010 |
| Impact of air pollution on floral morphology of Cassia siamea Lamk. SV Chauhan, B Chaurasia, A Rana Journal of Environmental Biology 25 (3), 291-297, 2004 | 24 | 2004 |
| Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design RS Rathore, AK Rana Superlattices and Microstructures 110, 68-81, 2017 | 20 | 2017 |
| Four phase clocking rule for energy efficient digital circuits—An adiabatic concept RK Yadav, AK Rana, S Chauhan, D Ranka, K Yadav 2011 2nd International Conference on Computer and Communication Technology …, 2011 | 19 | 2011 |
| Analytical modelling and simulation of negative capacitance junctionless FinFET considering fringing field effects S Kaushal, AK Rana Superlattices and Microstructures 155, 106929, 2021 | 18 | 2021 |
| Performance evaluation of FD-SOI MOSFETs for different metal gate work function D Ranka, AK Rana, RK Yadav, K Yadav, D Giri arXiv preprint arXiv:1104.0824, 2011 | 18 | 2011 |
| An efficient 256-tap parallel FIR digital filter implementation using distributed arithmetic architecture A Nandal, T Vigneswarn, AK Rana, A Dhaka Procedia Computer Science 54, 605-611, 2015 | 16 | 2015 |
| Performance analysis of FD-SOI MOSFET with different gate spacer dielectric D Ranka, AK Rana, RK Yadav, D Giri Int. J. Comput. Appl 18 (5), 22-27, 2011 | 16 | 2011 |
| Leakage behavior of underlap FinFET structure: A simulation study G Saini, AK Rana, PK Pal, S Jadav 2010 International Conference on Computer and Communication Technology …, 2010 | 16 | 2010 |
| Negative capacitance junctionless FinFET for low power applications: an innovative approach S Kaushal, AK Rana Silicon 14 (12), 6719-6728, 2022 | 15 | 2022 |
| Strained Si: Opportunities and challenges in nanoscale MOSFET R Sharma, AK Rana 2015 IEEE 2nd International Conference on Recent Trends in Information …, 2015 | 15 | 2015 |
| Comparative study of digital inverter for CNTFET & CMOS technologies R Gupta, AK Rana 2013 Nirma University International Conference on Engineering (NUiCONE), 1-5, 2013 | 15 | 2013 |
| Performance evaluation of negative capacitance junctionless FinFET under extreme length scaling S Kaushal, AK Rana, R Sharma Silicon, 1-10, 2021 | 14 | 2021 |
| Design and structural optimization of junctionless FinFET with Gaussian-doped channel S Kaundal, AK Rana Journal of Computational Electronics 17, 637-645, 2018 | 14 | 2018 |
| Impact of high-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET R Sharma, RS Rathore, AK Rana Journal of Circuits, Systems and Computers 27 (04), 1850063, 2018 | 14 | 2018 |
