| Method and system for speech recognition NC Badavne, TM Parng, PY Yeh, VKB Yadaiah US Patent App. 13/705,168, 2013 | 152 | 2013 |
| FPGA based high performance double-precision matrix multiplication VBY Kumar, S Joshi, SB Patkar, H Narayanan International journal of parallel programming 38, 322-338, 2010 | 82 | 2010 |
| FPGA Based High Performance Double-Precision Matrix Multiplication VBY Kumar, S Joshi, SB Patkar, H Narayanan VLSI Design, 2009 22nd International Conference on, 341 - 346, 2009 | 82 | 2009 |
| Post-quantum secure boot VBY Kumar, N Gupta, A Chattopadhyay, M Kasper, C Krauß, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 27 | 2020 |
| Itus: A secure risc-v system-on-chip VBY Kumar, A Chattopadhyay, J Haj-Yahya, A Mendelson 2019 32nd IEEE International System-on-Chip Conference (SOCC), 418-423, 2019 | 18 | 2019 |
| A Novel Duplication-Based Countermeasure to Statistical Ineffective Fault Analysis A Baksi, A Baksi Classical and Physical Security of Symmetric Key Cryptographic Algorithms …, 2022 | 10 | 2022 |
| Towards Designing a Secure RISC-V System-on-Chip: ITUS VBY Kumar, S Deb, N Gupta, S Bhasin, J Haj-Yahya, A Chattopadhyay, ... Journal of Hardware and Systems Security 4 (4), 329–342, 2020 | 10 | 2020 |
| Aero: Design space exploration framework for resource-constrained cnn mapping on tile-based accelerators S Yang, D Bhattacharjee, VBY Kumar, S Chatterjee, S De, P Debacker, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 6 | 2022 |
| Framework for application mapping over packet-switched network of fpgas: Case studies VBY Kumar, P Engineer, M Datar, Y Turakhia, S Agarwal, S Diwale, ... arXiv preprint arXiv:1508.06823, 2015 | 6 | 2015 |
| Relaxation based circuit simulation acceleration over CPU-FPGA VBY Kumar, K Dhiman, M Datar, A Pacharne, H Narayanan, SB Patkar 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 4 | 2016 |
| Feeding three birds with one scone: A generic duplication based countermeasure to fault attacks A Baksi, S Bhasin, J Breier, A Chattopadhyay, VBY Kumar 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 561-564, 2021 | 3 | 2021 |
| Secure Your SoC: Building System-on-Chip Designs for Security S Bhasin, TE Carlson, A Chattopadhyay, VBY Kumar, A Mendelson, ... | 1 | 2020 |
| Recruiting Fault Tolerance Techniques for Microprocessor Security VBY Kumar, S Deb, R Kumar, M Khairallah, A Chattopadhyay, ... 2019 IEEE 28th Asian Test Symposium (ATS), 80-805, 2019 | 1 | 2019 |
| Parallel two step random walk algorithm to analyze VLSI power grid networks S Dash, V Bangera, VBY Kumar, G Trivedi, SB Patkar 2015 19th International Symposium on VLSI Design and Test, 1-2, 2015 | 1 | 2015 |
| FPGA-based Implementation of M4RM for Matrix Multiplication over GF (2) V Kumar, VBY Kumar, SB Patkar 18th International Symposium on VLSI Design and Test, 1-2, 2014 | 1 | 2014 |
| Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems J Porwal, S Diwale, VBY Kumar, SB Patkar Technical Papers of 2014 International Symposium on VLSI Design, Automation …, 2014 | 1 | 2014 |
| Lightweight Forth Programmable NoCs VBY Kumar, D Shah, M Datar, SB Patkar 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | | 2018 |
| Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping VBY Kumar, S Maity, SB Patkar 2014 IEEE 32nd International Conference on Computer Design (ICCD), 464-469, 2014 | | 2014 |
| Hardware-software Scalable Architectures for Gaussian Elimination over GF (2) and Higher Galois Fields. P Saxena, VBY Kumar, D Singh, H Narayanan, SB Patkar PECCS, 195-201, 2013 | | 2013 |
| Understanding Trends: A Qualitative Approach to Trend Identification and their Statistical Significance A Kumar, S Liess, J Kawale, V Kumar, S Chatterjee AGU Fall Meeting Abstracts 2011, NG51C-1669, 2011 | | 2011 |
