Kanad Basu
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
Processor description languages
P Mishra, N Dutt
Elsevier, 2011
1542011
Lossless data compression and real-time decompression
P Mishra, SW Seong, K Basu, W Wang, X Qin, C Murthy
US Patent App. 12/682,808, 2010
1522010
RATS: Restoration-aware trace signal selection for post-silicon validation
K Basu, P Mishra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (4), 605-613, 2012
832012
Test data compression using efficient bitmask and dictionary selection methods
K Basu, P Mishra
IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009
782009
Efficient trace signal selection for post silicon validation and debug
K Basu, P Mishra
2011 24th Internatioal Conference on VLSI Design, 352-357, 2011
722011
Efficient trace signal selection for post silicon validation and debug
K Basu, P Mishra
2011 24th Internatioal Conference on VLSI Design, 352-357, 2011
722011
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator
JJ Zhang, T Gu, K Basu, S Garg
2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018
532018
NIST Post-Quantum CryptographyA Hardware Evaluation Study
K Basu, D Soni, M Nabeel, R Karri
https://eprint.iacr.org/2019/047.pdf, 2019
422019
Efficient combination of trace and scan signals for post silicon validation and debug
K Basu, P Mishra, P Patra
2011 IEEE International Test Conference, 1-8, 2011
362011
Efficient trace data compression using statically selected dictionary
K Basu, P Mishra
29th VLSI Test Symposium, 14-19, 2011
262011
Dynamic selection of trace signals for post-silicon debug
K Basu, P Mishra, P Patra, A Nahir, A Adir
2013 14th International Workshop on Microprocessor Test and Verification, 62-67, 2013
212013
Fault-tolerant Systolic Array Based Accelerators for Deep Neural Network Execution
J Zhang, K Basu, S Garg
IEEE Design and Test, 2019
202019
CAD-Base: An Attack Vector into the Electronics Supply Chain.
K Basu, S Saeed, C Pilato, M Ashraf, M Nabeel, ...
ACM Transactions on Design Automation of Embedded Systems, 2019
202019
A Theoretical Study of Hardware Performance Counters-based Malware Detection
K Basu, P Krishnamurthy, F Khorrami, R Karri
IEEE Transactions on Information Forensics and Security, 2020
172020
A novel test-data compression technique using application-aware bitmask and dictionary selection methods
K Basu, P Mishra
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 83-88, 2008
162008
Post-Silicon Validation and Debug
P Mishra, F Farahmandi
Springer International Publishing, 2019
142019
A Hardware Evaluation Study of NIST Post-Quantum Cryptographic Signature schemes
D Soni, K Basu, M Nabeel, R Karri
Second-PQC-Standardization-Conference, 2019
132019
Observability-aware directed test generation for soft errors and crosstalk faults
K Basu, P Mishra, P Patra
2013 26th International Conference on VLSI Design and 2013 12th …, 2013
102013
PREEMPT: PReempting Malware by Examining Embedded Processor Traces
K Basu, R Elnaggar, K Chakrabarty, R Karri
ACM/IEEE International Conference on Design Automation Conference, 2019
92019
Black-Hat High-Level Synthesis: Myth or Reality?
C Pilato, K Basu, F Regazzoni, R Karri
IEEE Transactions on VLSI Systems, 2019
92019
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