Hyungjun Kim
Hyungjun Kim
Verified email at postech.ac.kr - Homepage
Cited by
Cited by
Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems
S Lim, C Sung, H Kim, T Kim, J Song, JJ Kim, H Hwang
IEEE Electron Device Letters 39 (2), 312-315, 2018
Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware
T Kim, H Kim, J Kim, JJ Kim
IEEE Electron Device Letters 38 (9), 1228-1231, 2017
Effect of conductance linearity and multi-level cell characteristics of TaOx-based synapse device on pattern recognition accuracy of neuromorphic system
C Sung, S Lim, H Kim, T Kim, K Moon, J Song, JJ Kim, H Hwang
Nanotechnology 29 (11), 115203, 2018
Deep neural network optimized to resistive memory with nonlinear current-voltage characteristics
H Kim, T Kim, J Kim, JJ Kim
ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (2), 15, 2018
Input-splitting of large neural networks for power-efficient accelerator with resistive crossbar memory array
Y Kim, H Kim, D Ahn, JJ Kim
Proceedings of the International Symposium on Low Power Electronics and …, 2018
BitBlade: Area and energy-efficient precision-scalable neural network accelerator with bitwise summation
S Ryu, H Kim, W Yi, JJ Kim
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations
H Kim, K Kim, J Kim, JJ Kim
arXiv preprint arXiv:2002.06517, 2020
Zero-shifting Technique for Deep Neural Network Training on Resistive Cross-point Arrays
H Kim, M Rasch, T Gokmen, T Ando, H Miyazoe, JJ Kim, J Rozen, S Kim
arXiv preprint arXiv:1907.10228, 2019
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array
J Kim, J Koo, T Kim, Y Kim, H Kim, S Yoo, JJ Kim
2019 Symposium on VLSI Circuits, C118-C119, 2019
In-memory batch-normalization for resistive memory based binary neural network hardware
H Kim, Y Kim, JJ Kim
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
Y Kim, H Kim, JJ Kim
arXiv preprint arXiv:1811.02187, 2018
Alignment Techniques to Match Symmetry Point as Zero-Weight Point in Analog Crosspoint Arrays
S Kim, H Kim, T Gokmen, M Rasch
US Patent App. 16/158,056, 2020
A 44.1 TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS
S Ryu, H Kim, W Yi, J Koo, E Kim, Y Kim, T Kim, JJ Kim
2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020
BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function
H Kim, Y Kim, S Ryu, JJ Kim
arXiv preprint arXiv:1903.09807, 2019
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