| Stacked memory device system interconnect directory-based cache coherence methodology J Leidel, RC Murphy US Patent 10,838,865, 2020 | 393 | 2020 |
| Virtual address table JD Leidel, KB Wheeler US Patent 9,910,787, 2018 | 243 | 2018 |
| Multidimensional contiguous memory allocation JD Leidel, K Wadleigh US Patent 9,940,026, 2018 | 181 | 2018 |
| Virtual register file JD Leidel, GC Rogers US Patent 10,049,054, 2018 | 120 | 2018 |
| Target architecture determination JD Leidel US Patent 10,140,104, 2018 | 106 | 2018 |
| Extreme heterogeneity 2018-productive computational science in the era of extreme heterogeneity: Report for DOE ASCR workshop on extreme heterogeneity JS Vetter, R Brightwell, M Gokhale, P McCormick, R Ross, J Shalf, ... USDOE Office of Science (SC), Washington, DC (United States), 2018 | 72 | 2018 |
| Systems and methods for selectively controlling multithreaded execution of executable code segments JD Leidel, KR Wadleigh, J Bolding, T Brewer, DE Walker US Patent 10,430,190, 2019 | 58 | 2019 |
| HMC-sim: A simulation framework for hybrid memory cube devices JD Leidel, Y Chen Parallel Processing Letters 24 (04), 1442002, 2014 | 44 | 2014 |
| Hmc-sim-2.0: A simulation platform for exploring custom memory cube operations JD Leidel, Y Chen 2016 IEEE International Parallel and Distributed Processing Symposium …, 2016 | 39 | 2016 |
| In-memory intelligence T Finkbeiner, G Hush, T Larsen, P Lea, J Leidel, T Manning IEEE Micro 37 (4), 30-38, 2017 | 32 | 2017 |
| Apparatuses and methods for memory alignment JD Leidel US Patent 10,423,353, 2019 | 24 | 2019 |
| Translation lookaside buffer in memory JD Leidel, RC Murphy US Patent 10,007,435, 2018 | 18 | 2018 |
| Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device JD Leidel US Patent 9,558,143, 2017 | 16 | 2017 |
| xbgas: A global address space extension on risc-v for high performance computing X Wang, JD Leidel, B Williams, A Ehret, M Mark, MA Kinsy, Y Chen 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2021 | 15 | 2021 |
| PIMS: A lightweight processing-in-memory accelerator for stencil computations J Li, X Wang, A Tumeo, B Williams, JD Leidel, Y Chen Proceedings of the International Symposium on Memory Systems, 41-52, 2019 | 14 | 2019 |
| CHOMP: a framework and instruction set for latency tolerant, massively multithreaded processors JD Leidel, K Wadleigh, J Bolding, T Brewer, D Walker 2012 SC Companion: High Performance Computing, Networking Storage and …, 2012 | 12 | 2012 |
| Concurrent dynamic memory coalescing on GoblinCore-64 architecture X Wang, JD Leidel, Y Chen Proceedings of the Second International Symposium on Memory Systems, 177-187, 2016 | 11 | 2016 |
| Extreme Heterogeneity 2018-Productive Computational Science in the Era of Extreme Heterogeneity: Report for DOE ASCR Workshop on Extreme Heterogeneity.(12 2018) JS Vetter, R Brightwell, M Gokhale, P McCormick, R Ross, J Shalf, ... Google Scholar Google Scholar Cross Ref Cross Ref, 2018 | 9 | 2018 |
| MAC: Memory access coalescer for 3D-stacked memory X Wang, A Tumeo, JD Leidel, J Li, Y Chen Proceedings of the 48th International Conference on Parallel Processing, 1-10, 2019 | 8 | 2019 |
| xbgas: Toward a risc-v isa extension for global, scalable shared memory JD Leidel, X Wang, F Conlon, Y Chen, D Donofrio, F Fatollahi-Fard, ... Proceedings of the Workshop on Memory Centric High Performance Computing, 22-26, 2018 | 8 | 2018 |
Yong ChenTexas Tech UniversityVerified email at ttu.edu
