Yong Li
Title
Cited by
Cited by
Year
Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs
Y Zhang, X Wang, Y Li, AK Jones, Y Chen
81*
Compiler-assisted data distribution for chip multiprocessors
Y Li, R Melhem, A Abousamra, AK Jones
2010 19th International Conference on Parallel Architectures and Compilation …, 2010
562010
A software approach for combating asymmetries of non-volatile memories
Y Li, Y Chen, AK Jones
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
492012
Read performance: The newest barrier in scaled STT-RAM
AKJ Y Zhang, Y Li, Z Sun, H Li, Y Chen
IEEE, 2015
40*2015
Going vertical in memory management: Handling multiplicity by multi-policy
L Liu, Y Li, Z Cui, Y Bao, M Chen, C Wu
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
392014
Practically private: Enabling high performance cmps through compiler-assisted data classification
Y Li, R Melhem, AK Jones
Proceedings of the 21st international conference on Parallel architectures …, 2012
372012
Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random
HYCW Lei Liu, Yong Li, Chen Ding
IEEE Transactions on Computers, 2015
272015
Multilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting
AKJ Haifeng Xu, Yong Li, Rami Melhem
25*
BPM/BPM+ Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems
L Liu, Z Cui, Y Li, Y Bao, M Chen, C Wu
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-28, 2014
222014
C1C: A configurable, compiler-guided STT-RAM L1 cache
Y Li, Y Zhang, H Li, Y Chen, AK Jones
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-22, 2013
192013
Memos: A full hierarchy hybrid memory management framework
L Liu, H Yang, Y Li, M Xie, L Li, C Wu
2016 IEEE 34th International Conference on Computer Design (ICCD), 368-371, 2016
172016
Prefetching techniques for STT-RAM based last-level cache in CMP systems
M Mao, G Sun, Y Li, AK Jones, Y Chen
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, 67-72, 2014
162014
PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs
Y Li, R Melhem, AK Jones
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-21, 2013
162013
Space oblivious compression: Power reduction for non-volatile main memories
Y Li, H Xu, R Melhem, AK Jones
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 217-220, 2015
132015
ContextPreRF: Enhancing the performance and energy of GPUs with nonuniform register access
M Moeng, H Xu, R Melhem, AK Jones
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 343-347, 2015
102015
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures
X Liu, Y Li, Y Zhang, AK Jones, Y Chen
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 355-360, 2014
92014
Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors
Y Li, A Abousamra, R Melhem, A Jones
Parallel and Distributed Systems, IEEE Transactions on, 1-1, 2011
82011
Cross-layer techniques for optimizing systems utilizing memories with asymmetric access characteristics
Y Li, AK Jones
2012 IEEE Computer Society Annual Symposium on VLSI, 404-409, 2012
72012
Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors
Y Li, R Melhem, A Jones
IEEE IEEE Computer Architecture Letters, 2011
62011
A practical data classification framework for scalable and high performance chip-multiprocessors
Y Li, R Melhem, AK Jones
IEEE Transactions on Computers 63 (12), 2905-2918, 2013
52013
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Articles 1–20