| The negative bias temperature instability in MOS devices: A review JH Stathis, S Zafar Microelectronics Reliability 46 (2-4), 270-286, 2006 | 502 | 2006 |
| Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks S Zafar, A Callegari, E Gusev, MV Fischetti Journal of Applied physics 93 (11), 9298-9303, 2003 | 385 | 2003 |
| Ultrathin high-K gate stacks for advanced CMOS devices EP Gusev, DA Buchanan, E Cartier, A Kumar, D DiMaria, S Guha, ... Electron Devices Meeting, 2001. IEDM'01. Technical Digest. International, 20 …, 2001 | 378 | 2001 |
| Threshold voltage instabilities in high-/spl kappa/gate dielectric stacks S Zafar, A Kumar, E Gusev, E Cartier IEEE Transactions on Device and Materials Reliability 5 (1), 45-64, 2005 | 349 | 2005 |
| A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates S Zafar, Y Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 23-25, 2006 | 285 | 2006 |
| Charge trapping in ultrathin hafnium oxide WJ Zhu, TP Ma, S Zafar, T Tamagawa IEEE Electron Device Letters 23 (10), 597-599, 2002 | 205 | 2002 |
| The electronic conduction mechanism in barium strontium titanate thin films S Zafar, RE Jones, B Jiang, B White, V Kaushik, S Gillespie Applied physics letters 73 (24), 3533-3535, 1998 | 203 | 1998 |
| Oxygen vacancy mobility determined from current measurements in thin films S Zafar, RE Jones, B Jiang, B White, P Chu, D Taylor, S Gillespie Applied physics letters 73 (2), 175-177, 1998 | 199 | 1998 |
| Memory device that includes passivated nanoclusters and method for manufacture R Muralidhar, CK Subramanian, S Madhukar, BE White, MA Sadd, S Zafar, ... US Patent 6,297,095, 2001 | 179 | 2001 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| Charge trapping in high k gate dielectric stacks S Zafar, A Callegari, E Gusev, MV Fischetti Digest. International Electron Devices Meeting,, 517-520, 2002 | 122 | 2002 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 119 | 2007 |
| Investigation of bulk and interfacial properties of thin film capacitors S Zafar, RE Jones, P Chu, B White, B Jiang, D Taylor, P Zurcher, ... Applied physics letters 72 (22), 2820-2822, 1998 | 115 | 1998 |
| Statistical mechanics based model for negative bias temperature instability induced degradation S Zafar Journal of applied physics 97 (10), 2005 | 112 | 2005 |
| Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond TC Chen, G Shahidi, S Guha, M Ieong, MP Chudzik, R Jammy, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 178-179, 2006 | 109 | 2006 |
| Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang Microelectronics reliability 49 (6), 642-649, 2009 | 102 | 2009 |
| Hydrogen-mediated model for defect metastability in hydrogenated amorphous silicon S Zafar, EA Schiff Physical Review B 40 (7), 5235, 1989 | 101 | 1989 |
| CVD tantalum compounds for FET get electrodes V Narayanan, F McFeely, K Milkove, J Yurkas, M Copel, P Jamison, ... US Patent App. 10/712,575, 2005 | 100 | 2005 |
| Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS) J Kedzierski, D Boyd, P Ronsheim, S Zafar, J Newbury, J Ott, C Cabral, ... IEEE International Electron Devices Meeting 2003, 13.3. 1-13.3. 4, 2003 | 100 | 2003 |
| A model for negative bias temperature instability (NBTI) in oxide and high/spl kappa/pFETs 13/spl times/-C6D8C7F5F2 S Zafar, BH Lee, J Stathis, A Callegari, T Ning Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 208-209, 2004 | 95* | 2004 |
