Takip et
Xiyuan  Tang
Xiyuan Tang
pku.edu.cn üzerinde doğrulanmış e-posta adresine sahip - Ana Sayfa
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
A 0.7-V 0.6- 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction
L Chen, X Tang, A Sanyal, Y Yoon, J Cong, N Sun
IEEE Journal of Solid-State Circuits 52 (5), 1388-1398, 2017
702017
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
X Tang, L Shen, B Kasap, X Yang, W Shi, A Mukherjee, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits, 2020
532020
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier
X Tang, B Kasap, L Shen, X Yang, W Shi, N Sun
2019 Symposium on VLSI Circuits, C140-C141, 2019
532019
Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout
B Xu, Y Lin, X Tang, S Li, L Shen, N Sun, DZ Pan
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
402019
A 10-b 800-MS/s time-interleaved SAR ADC with fast variance-based timing-skew calibration
J Song, K Ragab, X Tang, N Sun
IEEE Journal of Solid-State Circuits 52 (10), 2563-2575, 2017
362017
GeniusRoute: A new analog routing paradigm using generative neural network guidance
K Zhu, M Liu, Y Lin, B Xu, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
352019
Comparator common-mode variation effects analysis and its application in SAR ADCs
L Chen, A Sanyal, J Ma, X Tang, N Sun
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2014-2017, 2016
342016
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction
L Chen, X Tang, A Sanyal, Y Yoon, J Cong, N Sun
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015
332015
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping
J Liu, X Wang, Z Gao, M Zhan, X Tang, N Sun
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 158-160, 2020
292020
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence
B Xu, K Zhu, M Liu, Y Lin, S Li, X Tang, N Sun, DZ Pan
282019
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
J Liu, X Tang, W Zhao, L Shen, N Sun
IEEE Journal of Solid-State Circuits 55 (12), 3260-3270, 2020
262020
A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS
J Song, X Tang, N Sun
2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017
252017
A 0.95-mW 6-b 700-MS/s single-channel loop-unrolled SAR ADC in 40-nm CMOS
L Chen, K Ragab, X Tang, J Song, A Sanyal, N Sun
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (3), 244-248, 2016
252016
A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS
X Tang, L Chen, J Song, N Sun
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 413-416, 2016
242016
A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier
X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, S Li, ...
IEEE Journal of Solid-State Circuits 55 (12), 3248-3259, 2020
232020
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- M Structure
W Zhao, S Li, B Xu, X Yang, X Tang, L Shen, N Lu, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits 55 (3), 666-679, 2019
232019
9.5 a 13.5 b-ENOB second-order noise-shaping SAR with PVT-robust closed-loop dynamic amplifier
X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 162-164, 2020
212020
18.2 a 16fJ/Conversion-step time-domain two-step Capacitance-to-Digital converter
X Tang, S Li, L Shen, W Zhao, X Yang, R Williams, J Liu, Z Tan, N Hall, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 296-297, 2019
21*2019
A 0.04-mm20.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration
Y Yoon, K Lee, S Hong, X Tang, L Chen, N Sun
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015
202015
Towards decrypting the art of analog layout: Placement quality prediction via transfer learning
M Liu, K Zhu, J Gu, L Shen, X Tang, N Sun, DZ Pan
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 496-501, 2020
192020
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