| Modeling sigma-delta modulator non-idealities in SIMULINK (R) S Brigati, F Francesconi, P Malcovati, D Tonietto, A Baschirotto, ... 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 384-387, 1999 | 284 | 1999 |
| Integrated decision feedback equalizer and clock and data recovery D Tonietto, A Momtaz US Patent 7,822,113, 2010 | 83 | 2010 |
| High speed receive equalizer architecture A Momtaz, M Caresosa, D Chung, D Tonietto, G Yin, B Currivan, T Kolze, ... US Patent 7,623,600, 2009 | 70 | 2009 |
| 6.2 A 60Gb/s PAM-4 ADC-DSP transceiver in 7nm CMOS with SNR-based adaptive power scaling achieving 6.9 pJ/b at 32dB loss MA LaCroix, H Wong, YH Liu, H Ho, S Lebedev, P Krotnev, DA Nicolescu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 114-116, 2019 | 59 | 2019 |
| SERDES with jitter-based built-in self test (BIST) for adapting FIR filter coefficients D Tonietto, J Hogeboom US Patent 8,228,972, 2012 | 59 | 2012 |
| A smart sensor system for carbon monoxide detection GC Cardinali, L Dori, M Fiorini, I Sayago, G Faglia, C Perego, ... Smart sensor interfaces, 113-134, 1997 | 57 | 1997 |
| 8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2 MA LaCroix, E Chong, W Shen, E Nir, FA Musa, H Mei, MM Mohsenpour, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 132-134, 2021 | 46 | 2021 |
| A 3.3-V CMOS 10.7-MHz sixth-order bandpass/spl Sigma//spl Delta/modulator with 74-dB dynamic range P Cusinato, D Tonietto, F Stefani, A Baschirotto IEEE Journal of Solid-State Circuits 36 (4), 629-638, 2001 | 42 | 2001 |
| Bit stream conditioning circuit having adjustable PLL bandwidth D Tonietto, A Ghiasi US Patent 7,321,612, 2008 | 31 | 2008 |
| 30.5 A 1.41 pJ/b 56Gb/s PAM-4 wireline receiver employing enhanced pattern utilization CDR and genetic adaptation algorithms in 7nm CMOS S Shahramian, B Dehlaghi, J Liang, R Bespalko, D Dunwell, J Bailey, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 482-484, 2019 | 28 | 2019 |
| Bit stream linear equalizer with AGC loop D Tonietto, A Ghiasi US Patent 7,664,170, 2010 | 25 | 2010 |
| High speed receive equalizer architecture A Momtaz, M Caresosa, DK Chung, D Tonietto, G Yin, B Currivan, T Kolze, ... US Patent 7,974,337, 2011 | 24 | 2011 |
| Bit stream conditioning circuit having adjustable input sensitivity D Tonietto, A Ghiasi US Patent 7,317,769, 2008 | 24 | 2008 |
| A 112-Gb/s PAM-4 low-power nine-tap sliding-block DFE in a 7-nm FinFET wireline receiver J Bailey, H Shakiba, E Nir, G Marderfeld, P Krotnev, MA LaCroix, ... IEEE Journal of Solid-State Circuits 57 (1), 32-43, 2021 | 22 | 2021 |
| A 3.3 V CMOS 10.7 MHz 6th-order bandpass Σ Δ modulator with 78dB dynamic range D Tonietto, P Cusinato, F Stefani, A Baschirotto Proceedings of the 25th European Solid-State Circuits Conference, 78-81, 1999 | 22 | 1999 |
| Circuit and method for self trimming frequency acquisition D Tonietto, AM Bischof US Patent 6,807,225, 2004 | 21 | 2004 |
| Bit stream conditioning circuit having adjustable input sensitivity D Tonietto, A Ghiasi US Patent 8,014,471, 2011 | 19 | 2011 |
| System and method for programmably adjusting gain and frequency response in a 10-GigaBit ethernet/fibre channel system I Fujimori, D Tonietto US Patent 7,206,366, 2007 | 18 | 2007 |
| Eye mapping built-in self test (bist) method and apparatus J Hogeboom, D Tonietto US Patent App. 12/254,397, 2010 | 17 | 2010 |
| Sigma-delta processing in multisensor systems for carbon monoxide detection Y Liberali, F Maloberti, D Tonietto 1996 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 376-379, 1996 | 17 | 1996 |
