Takip et
Soo Han Choi
Soo Han Choi
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Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
Layout decomposition of self-aligned double patterning for 2D random logic patterning
Y Ban, A Miloslavsky, K Lucas, SH Choi, CH Park, DZ Pan
Design for Manufacturability through Design-Process Integration V 7974, 79740L, 2011
482011
Study of optical proximity effects using off-axis illumination with attenuated phase shift mask
CN Ahn, KH Baik, YS Lee, HE Kim, I Hur, YS Kim, JH Kim, SH Choi
Optical/Laser Microlithography VIII 2440, 222-239, 1995
231995
Categorized stitching guidance for triple-patterning technology
SH Choi, S Arikati, E Cilingir
US Patent 9,747,407, 2017
212017
A fast lithography verification framework for litho-friendly layout design
YC Ban, SH Choi, KH Lee, DH Kim, JS Hong, YH Kim, MH Yoo, JT Kong
Sixth international symposium on quality electronic design (isqed'05), 169-174, 2005
172005
MEEF-based correction to achieve OPC convergence of low-k1 lithography with strong OAI
SH Choi, AY Je, JS Hong, MH Yoo, JT Kong
Optical Microlithography XIX 6154, 61540P, 2006
142006
Smart gas sensor and noise properties of single ZnO nanowire
SH Choi, SM Yee, HJ Ji, JW Choi, YS Cho, GT Kim
Japanese journal of applied physics 48 (6S), 06FD13, 2009
122009
Effect of pattern density for contact windows in an attenuated phase shift mask
I Hur, JH Kim, IH Lee, HE Kim, CN Ahn, KH Baik, SH Choi
Optical/Laser Microlithography VIII 2440, 278-289, 1995
121995
Hybrid PPC methodology using multistep correction and implementation for the sub-100-nm node
SH Choi, JS Park, CH Park, WY Chung, I Kim, DH Kim, YH Kim, MH Yoo, ...
Optical Microlithography XVI 5040, 1176-1183, 2003
112003
System for analyzing mask topography and method of forming image using the system
SH Choi, YJ Chun, M Yoo, JH Choi, JS Hong
US Patent 8,045,787, 2011
102011
Mask for manufacturing a highly-integrated circuit device
CH Park, M Yoo, Y Kim, DH Kim, SH Choi
US Patent 6,998,199, 2006
10*2006
Simulation-based critical-area extraction and litho-friendly layout design for low k1 lithography
SH Choi, YC Ban, KH Lee, DH Kim, JS Hong, YH Kim, MH Yoo, JT Kong
Optical Microlithography XVII 5377, 713-720, 2004
102004
Categorized stitching guidance for triple-patterning technology
SH Choi, S Arikati, E Cilingir
US Patent 10,261,412, 2019
72019
Hybrid PPC methodology and implementation in the correction of etch proximity
CH Park, SU Rhie, SH Choi, DH Kim, JS Park, YH Kim, MH Yoo, JT Kong
Optical Microlithography XV 4691, 369-376, 2002
72002
Method for fabricating EEPROM with control gate in touch with select gate
KS Shin, SH Choi
US Patent 5,614,429, 1997
61997
Effective alignment technique and its implementation to enhance total overlay accuracy on highly reflective films
YH Min, SC Moon, HS Kim, KH Baik, SH Choi
Integrated Circuit Metrology, Inspection, and Process Control IX 2439, 287-297, 1995
61995
Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination
SH Choi, TH Park, E Kim, HJ Youn, DY Lee, YC Ban, AY Je, DH Kim, ...
Optical Microlithography XVIII 5754, 838-845, 2005
52005
EEPROM and method for fabricating the same
KS Shin, SH Choi
US Patent 5,710,735, 1998
51998
DFM based on layout restriction and process window verification for sub-60-nm memory devices
SH Choi, DH Jung, JS Hong, JH Choi, MH Yoo, JT Kong
Photomask and Next-Generation Lithography Mask Technology XIV 6607, 66071A, 2007
42007
Accurate gate CD control through the full-chip area using the dual model in the model-based OPC
JS Hong, CH Park, DH Kim, SH Choi, YC Ban, YH Kim, MH Yoo, JT Kong
Optical Microlithography XVII 5377, 571-580, 2004
42004
Assessments on process parameters' influences to the proximity correction
EM Lee, SW Lee, DY Lee, SH Choi, JO Park, SG Jung, GS Yeo, JH Lee, ...
Metrology, Inspection, and Process Control for Microlithography XVIII 5375 …, 2004
42004
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