Shreepad Panth
Shreepad Panth
intel.com üzerinde doğrulanmış e-posta adresine sahip
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
3D-MAPS: 3D massively parallel processor with stacked memory
DH Kim, K Athikulwongse, M Healy, M Hossain, M Jung, I Khorosh, ...
IEEE International Solid-State Circuits Conference, 2012
2042012
Design and CAD methodologies for low power gate-level monolithic 3D ICs
SA Panth, K Samadi, Y Du, SK Lim
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
1122014
3D floorplanning using 2D and 3D blocks
K Samadi, SA Panth, Y Du
US Patent 9,064,077, 2015
1012015
Power-performance study of block-level monolithic 3D-ICs considering inter-tier performance variations
S Panth, K Samadi, Y Du, SK Lim
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
712014
High-density integration of functional modules using monolithic 3D-IC technology
S Panth, K Samadi, Y Du, SK Lim
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 681-686, 2013
662013
Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)
DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ...
IEEE Transactions on Computers 64 (1), 112-125, 2013
622013
Clock distribution network for 3D integrated circuit
K Samadi, SA Panth, J Xie, Y Du
US Patent 9,098,666, 2015
612015
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
S Panth, K Samadi, Y Du, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
612015
Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro
K Samadi, SA Panth, Y Du, RP Gilmore
US Patent 10,192,813, 2019
542019
Fast and accurate thermal modeling and optimization for monolithic 3D ICs
SK Samal, S Panth, K Samadi, M Saedi, Y Du, SK Lim
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
432014
Shrunk-2-D: A physical design methodology to build commercial-quality monolithic 3-D ICs
S Panth, K Samadi, Y Du, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
402017
Scan test of die logic in 3-D ICs using TSV probing
B Noia, S Panth, K Chakrabarty, SK Lim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 317-330, 2014
342014
Design challenges and solutions for ultra-high-density monolithic 3D ICs
S Panth, S Samal, YS Yu, SK Lim
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014
312014
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores
DL Lewis, S Panth, X Zhao, SK Lim, HHS Lee
2011 IEEE 29th International Conference on Computer Design (ICCD), 90-95, 2011
232011
Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts
A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi
IEEE International Interconnect Technology Conference, 345-348, 2014
212014
Isonet: Hardware-based job queue management for many-core architectures
J Lee, C Nicopoulos, HG Lee, S Panth, SK Lim, J Kim
IEEE transactions on very large scale integration (VLSI) systems 21 (6 …, 2012
162012
Adaptive regression-based thermal modeling and optimization for monolithic 3-D ICs
SK Samal, S Panth, K Samadi, M Saeidi, Y Du, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
152016
Electrical coupling of monolithic 3-D inverters
YS Yu, S Panth, SK Lim
IEEE Transactions on Electron Devices 63 (8), 3346-3349, 2016
142016
TSV stress-aware ATPG for 3D stacked ICs
S Deutsch, K Chakrabarty, S Panth, SK Lim
2012 IEEE 21st Asian Test Symposium, 31-36, 2012
142012
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs
S Panth, SK Lim
29th VLSI Test Symposium, 26-31, 2011
142011
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Makaleler 1–20