Lingyi Liu
Lingyi Liu
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Title
Cited by
Cited by
Year
Efficient validation input generation in RTL by hybridized source code analysis
L Liu, S Vasudevan
2011 Design, Automation & Test in Europe, 1-6, 2011
722011
Integration of data mining and static analysis for hardware design verification
S Vasudevan, D Sheridan, L Liu
US Patent 9,021,409, 2015
592015
STAR: Generating input vectors for design validation by static analysis of RTL
L Liu, S Vasudevan
2009 IEEE International High Level Design Validation and Test Workshop, 32-37, 2009
332009
Low power processor design for wireless sensor network applications
Y Xu, L Liu, P Shen, T Lv, X Li
Proceedings. 2005 International Conference on Wireless Communications …, 2005
302005
Automatic generation of assertions from system level design using data mining
L Liu, D Sheridan, V Athavale, S Vasudevan
Ninth ACM/IEEE International Conference on Formal Methods and Models for …, 2011
262011
Word level feature discovery to enhance quality of assertion mining
L Liu, CH Lin, S Vasudevan
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 210-217, 2012
252012
Towards coverage closure: Using goldmine assertions for generating design validation stimulus
L Liu, D Sheridan, W Tuohy, S Vasudevan
2011 Design, Automation & Test in Europe, 1-6, 2011
242011
A technique for test coverage closure using goldmine
L Liu, D Sheridan, W Tuohy, S Vasudevan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
232012
A coverage guided mining approach for automatic generation of succinct assertions
D Sheridan, L Liu, H Kim, S Vasudevan
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
212014
Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL
L Liu, S Vasudevan
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1), 2014
192014
Observability statement coverage based on dynamic factored use-definition chains for functional verification
T Lv, JP Fan, XW Li, LY Liu
Journal of Electronic Testing 22 (3), 273-285, 2006
142006
Automatic generation of system level assertions from transaction level models
L Liu, S Vasudevan
Journal of Electronic Testing 29 (5), 669-684, 2013
132013
An observability branch coverage metric based on dynamic factored use-define chains
T Lv, L Liu, Y Zhao, H Li, X Li
2006 15th Asian Test Symposium, 89-94, 2006
122006
Diagnosing root causes of system level performance violations
L Liu, X Zhong, X Chen, S Vasudevan
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 295-302, 2013
72013
Generating concise assertions with complete coverage
CH Lin, L Liu, S Vasudevan
Proceedings of the 23rd ACM international conference on Great lakes …, 2013
32013
结合 ATPG 和 SAT 的无界模型检验前像计算方法
刘领一, 赵阳, 吕涛, 李华伟, 李晓维
计算机辅助设计与图形学学报 19 (003), 376-380, 2007
22007
Harmonizing data mining and static analysis to tackle hardware and system level verification
L Liu
University of Illinois at Urbana-Champaign, 2014
12014
Scaling RTL property checking using feasible path analysisand decomposition
L Liu, S Vasudevan
Proceedings of the 23rd ACM international conference on Great lakes …, 2013
12013
Scaling probabilistic timing verification of hardware using abstractions in design source code
JA Kumar, L Liu, S Vasudevan
2011 Formal Methods in Computer-Aided Design (FMCAD), 196-205, 2011
12011
A Comparative Study of Assertion Mining Algorithms in GoldMine
S Vasudevan, L Liu, S Hertz
Machine Learning in VLSI Computer-Aided Design, 609-645, 2019
2019
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