Xiuyuan Bi
Xiuyuan Bi
PhD candidate of Electrical and Computer Engineering, University of Pittsburgh
Verified email at pitt.edu
Title
Cited by
Cited by
Year
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Z Sun, X Bi, H Li, WF Wong, ZL Ong, X Zhu, W Wu
proceedings of the 44th annual IEEE/ACM international symposium on …, 2011
2462011
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
X Bi, Z Sun, H Li, W Wu
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 88-94, 2012
652012
Process variation aware data management for STT-RAM cache design
Z Sun, X Bi, H Li
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
532012
Unleashing the potential of MLC STT-RAM caches
X Bi, M Mao, D Wang, H Li
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 429-436, 2013
482013
STT-RAM cache hierarchy with multiretention MTJ designs
Z Sun, X Bi, H Li, WF Wong, X Zhu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6 …, 2013
402013
Design exploration of racetrack lower-level caches
Z Sun, X Bi, AK Jones, H Li
2014 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2014
242014
An efficient STT-RAM-based register file in GPU architectures
X Liu, M Mao, X Bi, H Li, Y Chen
The 20th Asia and South Pacific Design Automation Conference, 490-495, 2015
232015
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration
J Wang, P Roy, WF Wong, X Bi, H Li
2014 IEEE 32nd International Conference on Computer Design (ICCD), 133-138, 2014
232014
Array organization and data management exploration in racetrack memory
Z Sun, X Bi, W Wu, S Yoo, H Li
IEEE Transactions on Computers 65 (4), 1041-1054, 2014
212014
STT-RAM cell design considering CMOS and MTJ temperature dependence
X Bi, H Li, X Wang
IEEE Transactions on Magnetics 48 (11), 3821-3824, 2012
212012
Analysis and optimization of thermal effect on STT-RAM Based 3-D stacked cache design
X Bi, H Li, JJ Kim
2012 IEEE Computer Society Annual Symposium on VLSI, 374-379, 2012
152012
Spintronic memristor based temperature sensor design with CMOS current reference
X Bi, C Zhang, H Li, Y Chen, RE Pino
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
152012
STT-RAM designs supporting dual-port accesses
X Bi, MA Weldon, H Li
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 853-858, 2013
132013
Cross-layer optimization for multilevel cell STT-RAM caches
X Bi, M Mao, D Wang, HH Li
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (6 …, 2017
102017
Magnetic-assisted nondestructive self-reference sensing method for spin-transfer torque random access memory
Y Chen, E Eken, H Li, W Wen, X Bi
US Patent 9,627,024, 2017
32017
A pseudo-weighted sensing scheme for memristor based cross-point memory
Z Chen, L Zhang, X Bi, H Li
2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2013
32013
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ
Z Li, X Bi, HH Li, Y Chen, J Qin, P Guo, W Kong, W Zhan, X Han, H Zhang, ...
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
22016
The evolutionary spintronic technologies and their usage in high performance computing
HH Li, X Bi, Z Sun
2015 28th IEEE International System-on-Chip Conference (SOCC), 350-355, 2015
12015
STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices
HH Li, Z Sun, X Bi, WF Wong, X Zhu, W Wu
Emerging Memory Technologies, 169-199, 2014
12014
Spintronic devices: From memory to memristor
H Li, Z Sun, X Bi, B Wysocki
2012 IEEE 11th International Conference on Solid-State and Integrated …, 2012
12012
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