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Jorge Lagos
Jorge Lagos
imec.be üzerinde doğrulanmış e-posta adresine sahip - Ana Sayfa
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
J Lagos, B Hershberg, E Martens, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits 54 (2), 403 - 416, 2018
822018
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
J Lagos, B Hershberg, E Martens, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits 54 (3), 646 - 658, 2019
782019
Worst-case induced disturbances in digital and analog interchip interconnects by an external electromagnetic plane wave—Part I: Modeling and algorithm
JL Lagos, F Fiori
IEEE Transactions on Electromagnetic Compatibility 53 (1), 178-184, 2011
442011
3.1 A 3.2 GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
B Hershberg, D Dermit, B van Liempd, E Martens, N Markulic, J Lagos, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 58-60, 2019
432019
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
J Lagos, N Markulić, B Hershberg, D Dermit, M Shrivas, E Martens, ...
IEEE Journal of Solid-State Circuits 57 (4), 1112-1124, 2022
342022
A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion
B Hershberg, D Dermit, B van Liempd, E Martens, N Markulić, J Lagos, ...
IEEE Journal of Solid-State Circuits 56 (8), 2360-2374, 2021
302021
On-line software-based self-test of the address calculation unit in RISC processors
P Bernardi, L Ciganda, M de Carvalho, M Grosso, J Lagos-Benites, ...
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
302012
16.3 A Single-Channel 5.5 mW 3.3 GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation
Z Zheng, L Wei, J Lagos, E Martens, Y Zhu, CH Chan, J Craninckx, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 254-256, 2020
292020
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
B Hershberg, N Markulić, J Lagos, E Martens, D Dermit, J Craninckx
IEEE Journal of Solid-State Circuits 56 (4), 1227-1240, 2021
272021
3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm
B Hershberg, B van Liempd, N Markulic, J Lagos, E Martens, D Dermit, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 68-70, 2019
232019
Worst case-induced disturbances in microstrip interchip interconnects by an external electromagnetic plane wave—Part II: Analysis and validation
JL Lagos, F Fiori
IEEE Transactions on Electromagnetic Compatibility 53 (2), 491-500, 2011
212011
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier
Z Zheng, L Wei, J Lagos, E Martens, Y Zhu, CH Chan, J Craninckx, ...
IEEE Journal of Solid-State Circuits 57 (6), 1673-1683, 2021
122021
A versatile analog front-end for sensors based on piezoresistive silicon nanowire detection
O Leman, A Nikas, H Zhou, JL Lagos, BJ Vinchhi, J Hauer, G Jourdan, ...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 666-669, 2015
82015
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
LM Santana, E Martens, J Lagos, B Hershberg, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits 57 (7), 2068-2077, 2022
72022
A 83dB SNDR low power readout ASIC for piezoresistive nanogauge based gyroscopes
A Nikas, O Leman, H Zhou, JL Lagos, BJ Vinchhi, J Hauer
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2238-2241, 2016
72016
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs
B Hershberg, B van Liempd, N Markulić, J Lagos, E Martens, D Dermit, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2813-2826, 2021
62021
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC
L Wei, Z Zheng, N Markulic, J Lagos, E Martens, Y Zhu, CH Chan, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
42021
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems
J Lagos-Benites, M Grosso, MS Reorda, G Audisio, M Pipponzi, ...
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011
42011
A 47.5 MHz BW 4.7 mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
LM Santana, E Martens, J Lagos, B Hershberg, P Wambacq, J Craninckx
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
32021
A Low-Cost Emulation System for Fast Co-verification and Debug
J Lagos-Benites, M Grosso, L Sterpone, MS Reorda, G Audisio, ...
2011 Sixteenth IEEE European Test Symposium, 212-212, 2011
32011
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