| A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018 | 250 | 2018 |
| 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 225 | 2019 |
| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 179 | 2020 |
| A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019 | 155 | 2019 |
| 15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020 | 154 | 2020 |
| 16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hung, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 250-252, 2021 | 132 | 2021 |
| A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors X Si, WS Khwa, JJ Chen, JF Li, X Sun, R Liu, S Yu, H Yamauchi, Q Li, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11), 4172-4185, 2019 | 129 | 2019 |
| 14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy … J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020 | 125 | 2020 |
| Parallelizing SRAM arrays with customized bit-cell for binary neural networks R Liu, X Peng, X Sun, WS Khwa, X Si, JJ Chen, JF Li, MF Chang, S Yu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 112 | 2018 |
| A 4-Kb 1-to-8-bit configurable 6T SRAM-based computation-in-memory unit-macro for CNN-based AI edge processors YC Chiu, Z Zhang, JJ Chen, X Si, R Liu, YN Tu, JW Su, WH Huang, ... IEEE Journal of Solid-State Circuits 55 (10), 2790-2801, 2020 | 74 | 2020 |
| A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... IEEE Journal of Solid-State Circuits 56 (9), 2817-2831, 2021 | 73 | 2021 |
| A half-select disturb-free 11T SRAM cell with built-in write/read-assist scheme for ultralow-voltage operations Y He, J Zhang, X Wu, X Si, S Zhen, B Zhang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (10 …, 2019 | 60 | 2019 |
| Efficient and robust nonvolatile computing-in-memory based on voltage division in 2T2R RRAM with input-dependent sensing control L Wang, W Ye, C Dou, X Si, X Xu, J Liu, D Shang, J Gao, F Zhang, Y Liu, ... IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1640-1644, 2021 | 34 | 2021 |
| 15.4 A 5.99-to-691.1 TOPS/W tensor-train in-memory-computing processor using bit-level-sparsity-based optimization and variable-precision quantization R Guo, Z Yue, X Si, T Hu, H Li, L Tang, Y Wang, L Liu, MF Chang, Q Li, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 242-244, 2021 | 32 | 2021 |
| Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... IEEE Journal of Solid-State Circuits 57 (2), 609-624, 2021 | 27 | 2021 |
| A 28nm 64-kb 31.6-TFLOPS/W digital-domain floating-point-computing-unit and double-bit 6T-SRAM computing-in-memory macro for floating-point CNNs A Guo, X Si, X Chen, F Dong, X Pu, D Li, Y Zhou, L Ren, Y Xue, X Dong, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 128-130, 2023 | 25 | 2023 |
| STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ... IEEE Journal of Solid-State Circuits 57 (8), 2560-2573, 2022 | 24 | 2022 |
| A 55nm 1-to-8 bit configurable 6T SRAM based computing-in-memory unit-macro for CNN-based AI edge processors Z Zhang, JJ Chen, X Si, YN Tu, JW Su, WH Huang, JH Wang, WC Wei, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 217-218, 2019 | 21 | 2019 |
| 33.4 A 28nm 2Mb STT-MRAM computing-in-memory macro with a refined bit-cell and 22.4-41.5 TOPS/W for AI inference H Cai, Z Bian, Y Hou, Y Zhou, Y Guo, X Tian, B Liu, X Si, Z Wang, J Yang, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 500-502, 2023 | 19 | 2023 |
| A 8-b-precision 6T SRAM computing-in-memory macro using segmented-bitline charge-sharing scheme for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hong, ... IEEE Journal of Solid-State Circuits 58 (3), 877-892, 2022 | 19 | 2022 |
Meng-Fan ChangNational Tsing Hua University, TaiwanVerified email at ee.nthu.edu.tw
