| Double patterning technology friendly detailed routing M Cho, Y Ban, DZ Pan 2008 IEEE/ACM International Conference on Computer-Aided Design, 506-511, 2008 | 94 | 2008 |
| Flexible 2D layout decomposition framework for spacer-type double pattering lithography Y Ban, K Lucas, D Pan Proceedings of the 48th Design Automation Conference, 789-794, 2011 | 59 | 2011 |
| Standard cell layout regularity and pin access optimization considering middle-of-line W Ye, B Yu, DZO Pan, YC Ban, L Liebmann Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 289-294, 2015 | 55 | 2015 |
| Method And Apparatus For Determining Mask Layouts For A Spacer-Is-Dielectric Self-Aligned Double-Patterning Process Y Ban, K Lucas US Patent US 2012/0137261 A1, 2012 | 51 | 2012 |
| Layout decomposition of self-aligned double patterning for 2D random logic patterning Y Ban, A Miloslavsky, K Lucas, SH Choi, CH Park, DZ Pan Design for Manufacturability through Design-Process Integration V 7974, 158-172, 2011 | 49 | 2011 |
| ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction M Cho, K Yuan, Y Ban, DZ Pan Proceedings of the 45th annual Design Automation Conference, 504-509, 2008 | 38 | 2008 |
| Electrical impact of line-edge roughness on sub-45-nm node standard cells Y Ban, S Sundareswaran, DZ Pan Journal of Micro/Nanolithography, MEMS, and MOEMS 9 (4), 041206-041206-10, 2010 | 33 | 2010 |
| Dealing with IC manufacturability in extreme scaling B Yu, JR Gao, D Ding, Y Ban, J Yang, K Yuan, M Cho, DZ Pan Proceedings of the International Conference on Computer-Aided Design, 240-242, 2012 | 31 | 2012 |
| Electrical impact of line-edge roughness on sub-45nm node standard cell Y Ban, S Sundareswaran, R Panda, DZ Pan Design for Manufacturability through Design-Process Integration III 7275 …, 2009 | 24 | 2009 |
| Total sensitivity based DFM optimization of standard library cells Y Ban, S Sundareswaran, DZ Pan Proceedings of the 19th international symposium on Physical design, 113-120, 2010 | 20 | 2010 |
| ELIAD: Efficient lithography aware detailed routing algorithm with compact and macro post-OPC printability prediction M Cho, K Yuan, Y Ban, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 19 | 2009 |
| A fast lithography verification framework for litho-friendly layout design YC Ban, SH Choi, KH Lee, DH Kim, JS Hong, YH Kim, MH Yoo, JT Kong Sixth international symposium on quality electronic design (isqed'05), 169-174, 2005 | 17 | 2005 |
| Layout optimizations for double patterning lithography DZ Pan, J Yang, K Yuan, M Cho, Y Ban 2009 IEEE 8th International Conference on ASIC, 726-729, 2009 | 16 | 2009 |
| Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations Y Ban, Y Ma, DZ Pan, HJ Levinson Journal of Micro/Nanolithography, MEMS, and MOEMS 9 (4), 041211-041211-10, 2010 | 14 | 2010 |
| Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography Y Ban, DZ Pan Proceedings of the 47th Design Automation Conference, 408-411, 2010 | 13 | 2010 |
| Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell Y Ban, Y Ma, HJ Levinson, Y Deng, J Kye, DZ Pan Design for Manufacturability through Design-Process Integration IV 7641, 101-111, 2010 | 13 | 2010 |
| Modeling of layout aware line-edge roughness and poly optimization for leakage minimization Y Ban, DZ Pan IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011 | 12 | 2011 |
| Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip) Y Ban, C Choi, H Shin, Y Kang, WH Paik Design-Process-Technology Co-optimization for Manufacturability VIII 9053 …, 2014 | 10 | 2014 |
| Layout induced variability and manufacturability checks in FinFETs process Y Ban, J Sweis, P Hurat, Y Lai, Y Kang, WH Paik, W Xu, H Song Design-Process-Technology Co-optimization for Manufacturability VIII 9053 …, 2014 | 10 | 2014 |
| Simulation-based critical-area extraction and litho-friendly layout design for low k1 lithography SH Choi, YC Ban, KH Lee, DH Kim, JS Hong, YH Kim, MH Yoo, JT Kong Optical Microlithography XVII 5377, 713-720, 2004 | 10 | 2004 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at Austinece.utexas.edu üzerinde doğrulanmış e-posta adresine sahip
