Debapriya Basu Roy
Debapriya Basu Roy
Post Doctoral Fellow, EISEC, Technical University of Munich
Verified email at tum.de
Title
Cited by
Cited by
Year
Role of power grid in side channel attack and power-grid-aware secure design
X Wang, W Yueh, DB Roy, S Narasimhan, Y Zheng, S Mukhopadhyay, ...
Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013
402013
Tile before multiplication: An efficient strategy to optimize DSP multiplier for accelerating prime field ECC for NIST curves
DB Roy, D Mukhopadhyay, M Izumi, J Takahashi
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
262014
ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF(p)
DB Roy, P Das, D Mukhopadhyay
International Conference on Selected Areas in Cryptography, 161-177, 2015
242015
From theory to practice of private circuit: A cautionary note
DB Roy, S Bhasin, S Guilley, JL Danger, D Mukhopadhyay
2015 33rd IEEE International Conference on Computer Design (ICCD), 296-303, 2015
182015
Integrated sensor: a backdoor for hardware Trojan insertions?
XT Ng, Z Naj, S Bhasin, DB Roy, JL Danger, S Guilley
2015 Euromicro Conference on Digital System Design, 415-422, 2015
142015
Number “Not Used” Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates
P Ravi, DB Roy, S Bhasin, A Chattopadhyay, D Mukhopadhyay
International Workshop on Constructive Side-Channel Analysis and Secure …, 2019
132019
FPGA implementation of IP protection through visual information hiding
A Basu, DB Roy, D Banerjee, A Sengupta, A Saha, TS Das, SK Sarkar
International Journal of Engineering Science and Technology 3 (5), 4191-4199, 2011
122011
Reconfigurable LUT: A double edged sword for security-critical applications
DB Roy, S Bhasin, S Guilley, JL Danger, D Mukhopadhyay, XT Ngo, ...
International Conference on Security, Privacy, and Applied Cryptography …, 2015
112015
High-speed implementation of ECC scalar multiplication in GF (p) for generic Montgomery curves
DB Roy, D Mukhopadhyay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (7 …, 2019
92019
Using Tweaks To Design Fault Resistant Ciphers (Full Version)
S Patranabis, DB Roy, D Mukhopadhyay
Proceedings of the Computing Frontiers Conference, 402-408, 2017
92017
Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems.
S Sonar, DB Roy, RS Chakraborty, D Mukhopadhyay
IACR Cryptol. ePrint Arch. 2016, 182, 2016
92016
A framework to counter statistical ineffective fault analysis of block ciphers using domain transformation and error correction
S Saha, D Jap, DB Roy, A Chakraborty, S Bhasin, D Mukhopadhyay
IEEE Transactions on Information Forensics and Security 15, 1905-1919, 2019
72019
SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC
M Alam, DB Roy, S Bhattacharya, V Govindan, RS Chakraborty, ...
2016 ACM/IEEE International Conference on Formal Methods and Models for …, 2016
72016
Lightweight design-for-security strategies for combined countermeasures against side channel and fault analysis in IoT applications
S Patranabis, DB Roy, A Chakraborty, N Nagar, A Singh, ...
Journal of Hardware and Systems Security 3 (2), 103-131, 2019
62019
Shuffling across rounds: A lightweight strategy to counter side-channel attacks
S Patranabis, DB Roy, PK Vadnala, D Mukhopadhyay, S Ghosh
2016 IEEE 34th International Conference on Computer Design (ICCD), 440-443, 2016
62016
Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance.
P Das, DB Roy, D Mukhopadhyay
IACR Cryptol. ePrint Arch. 2015, 925, 2015
62015
Fault Template Attacks on Block Ciphers Exploiting Fault Propagation
S Saha, A Bag, DB Roy, S Patranabis, D Mukhopadhyay
Annual International Conference on the Theory and Applications of …, 2020
52020
Combining puf with rluts: a two-party pay-per-device ip licensing scheme on fpgas
DB Roy, S Bhasin, I Nikolić, D Mukhopadhyay
ACM Transactions on Embedded Computing Systems (TECS) 18 (2), 1-22, 2019
52019
Post Quantum ECC on FPGA Platform.
DB Roy, D Mukhopadhyay
IACR Cryptol. ePrint Arch. 2019, 568, 2019
52019
CC meets FIPS: A hybrid test methodology for first order side channel analysis
DB Roy, S Bhasin, S Guilley, A Heuser, S Patranabis, D Mukhopadhyay
IEEE Transactions on Computers 68 (3), 347-361, 2018
52018
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Articles 1–20