| NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning PY Chen, X Peng, S Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 428 | 2018 |
| NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures PY Chen, X Peng, S Yu 2017 IEEE International Electron Devices Meeting (IEDM), 6.1. 1-6.1. 4, 2017 | 323 | 2017 |
| DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies X Peng, S Huang, Y Luo, X Sun, S Yu 2019 IEEE international electron devices meeting (IEDM), 32.5. 1-32.5. 4, 2019 | 243 | 2019 |
| XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks X Sun, S Yin, X Peng, R Liu, J Seo, S Yu 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 231 | 2018 |
| Compute-in-memory chips for deep learning: Recent trends and prospects S Yu, H Jiang, S Huang, X Peng, A Lu IEEE circuits and systems magazine 21 (3), 31-56, 2021 | 179 | 2021 |
| A methodology to improve linearity of analog RRAM for neuromorphic computing W Wu, H Wu, B Gao, P Yao, X Zhang, X Peng, S Yu, H Qian 2018 IEEE symposium on VLSI technology, 103-104, 2018 | 166 | 2018 |
| DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training X Peng, S Huang, H Jiang, A Lu, S Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 150 | 2020 |
| Parallelizing SRAM arrays with customized bit-cell for binary neural networks R Liu, X Peng, X Sun, WS Khwa, X Si, JJ Chen, JF Li, MF Chang, S Yu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 112 | 2018 |
| Fully parallel RRAM synaptic array for implementing binary neural network with (+ 1,− 1) weights and (+ 1, 0) neurons X Sun, X Peng, PY Chen, R Liu, J Seo, S Yu 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 574-579, 2018 | 104 | 2018 |
| Optimizing weight mapping and data flow for convolutional neural networks on RRAM based processing-in-memory architecture X Peng, R Liu, S Yu 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 81 | 2019 |
| Optimizing weight mapping and data flow for convolutional neural networks on processing-in-memory architectures X Peng, R Liu, S Yu IEEE Transactions on Circuits and Systems I: Regular Papers 67 (4), 1333-1343, 2019 | 65 | 2019 |
| RRAM for compute-in-memory: From inference to training S Yu, W Shim, X Peng, Y Luo IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2753-2765, 2021 | 62 | 2021 |
| Compute-in-memory with emerging nonvolatile-memories: Challenges and prospects S Yu, X Sun, X Peng, S Huang 2020 ieee custom integrated circuits conference (cicc), 1-4, 2020 | 60 | 2020 |
| Design guidelines of RRAM based neural-processing-unit: A joint device-circuit-algorithm analysis W Zhang, X Peng, H Wu, B Gao, H He, Y Zhang, S Yu, H Qian Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 57 | 2019 |
| CIMAT: A compute-in-memory architecture for on-chip training based on transpose SRAM arrays H Jiang, X Peng, S Huang, S Yu IEEE Transactions on Computers 69 (7), 944-954, 2020 | 47 | 2020 |
| Cross-point memory design challenges and survey of selector device characteristics X Peng, R Madler, PY Chen, S Yu Journal of Computational Electronics 16, 1167-1174, 2017 | 45 | 2017 |
| NeuroSim simulator for compute-in-memory hardware accelerator: Validation and benchmark A Lu, X Peng, W Li, H Jiang, S Yu Frontiers in artificial intelligence 4, 659060, 2021 | 36 | 2021 |
| Structured pruning of RRAM crossbars for efficient in-memory computing acceleration of deep neural networks J Meng, L Yang, X Peng, S Yu, D Fan, JS Seo IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1576-1580, 2021 | 36 | 2021 |
| Computing-in-memory with SRAM and RRAM for binary neural networks X Sun, R Liu, X Peng, S Yu 2018 14th IEEE International Conference on Solid-State and Integrated …, 2018 | 34 | 2018 |
| Design considerations of selector device in cross-point RRAM array for neuromorphic computing J Woo, X Peng, S Yu 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 34 | 2018 |
Shimeng YuGeorgia Institute of Technology, Professor of ECEVerified email at ece.gatech.edu
