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Sajjad Parvin
Sajjad Parvin
Verified email at uni-bremen.de
Title
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Cited by
Year
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
S Parvin, T Krachenfels, S Tajik, JP Seifert, FS Torres, R Drechsler
Asia and South Pacific Design Automation Conference (ASP-DAC), 2022
92022
Efficient time-multiplexed realization of feedforward artificial neural networks
L Aksoy, S Parvin, ME Nojehdeh, M Altun
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
72020
Perfect concurrent fault detection in CMOS Logic circuits using parity preservative reversible gates
S Parvin, M Altun
IEEE Access 7, 163939-163947, 2019
72019
Trojan-D2: Post-layout design and detection of stealthy hardware trojans-a RISC-V case study
S Parvin, M Goli, FS Torres, R Drechsler
Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023
62023
Exploiting reversible computing for latent-fault-free error detecting/correcting CMOS circuits
M Altun, S Parvin, MH Cilasun
IEEE Access 6, 74475-74484, 2018
62018
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks
ME Nojehdeh, S Parvin, M Altun
IEEE Computer Society Annual Symposium on VLSI, 2021
22021
Implementation of CMOS logic circuits with perfect fault detection using preservative reversible gates
S Parvin, M Altun
2019 IEEE 25th International Symposium on On-Line Testing and Robust System …, 2019
22019
Hidden in Plain Sight: A Detailed Investigation of Selectively Increasing Local Density to Camouflage and Robustify Against Optical Probing Attacks
S Parvin, CK Jha, S Ahmadi-Pours, FS Torres, R Drechsler
2023 IEEE International Test Conference India (ITC India), 1-6, 2023
12023
Efficient Hardware Realizations of Feedforward Artificial Neural Networks
ME Nojehdeh, S Parvin, M Altun
arXiv preprint arXiv:2108.02073, 2021
12021
MarliK 2016 team description paper
N Nozari, OH Masouleh, SJ Fazel, S Nazari, A Eskandarzadeh, ...
RoboCup2016, Leipzig, Germany, 2016
12016
Hidden Cost of Circuit Design with RFETs
S Parvin, CK Jha, FS Torres, R Drechsler
2024
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core
S Parvin, S Ahmadi-Pour, CK Jha, FS Torres, R Drechsler
2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS …, 2023
2023
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing
S Parvin, M Goli, T Krachenfels, S Tajik, JP Seifert, FS Torres, R Drechsler
IEEE Computer Society Annual Symposium on VLSI, 2023
2023
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
S Parvin, M Goli, FS Torres, R Drechsler
Design, Automation and Test in Europe Conference (DATE), 2023
2023
Perfect detection of concurrent faults in CMOS circuits by exploiting reversible and preservative gates
M Altun, S Parvin
US Patent 11,307,252, 2022
2022
OPTI-RISK: Design of an Optical Probing Attack Hardened RISC-V Core with an Industrially Compatible CMOS Gate Library
S Parvin, S Ahmadi-Pour, C Kumar Jha, F Sill Torres, R Drechsler
5th RISC-V Activity Workshop, 2022
2022
How Secure Is A Circuit Against Optical Probing? Developed Countermeasures, In Progress Countermeasures Development, and the Future Works
S Parvin, FS Torres, R Drechsler
11th 2022 International Workshop on Cryptography, Robustness, and Provably …, 2022
2022
Efficient Hardware Realizations of Feedforward Artificial Neural Networks
M Esmali Nojehdeh, S Parvin, M Altun
arXiv e-prints, arXiv: 2108.02073, 2021
2021
A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks
S Parvin, M Altun
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 406-411, 2021
2021
A Study on Hardware-Aware Training Techniques
S Parvin, M Altun
IEEE Computer Society Annual Symposium on VLSI, 2021
2021
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