| A high-performance droplet routing algorithm for digital microfluidic biochips M Cho, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 182* | 2008 |
| BoxRouter: A new global router based on box expansion and progressive ILP M Cho, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 144 | 2007 |
| BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router M Cho, K Lu, K Yuan, DZ Pan 2007 IEEE/ACM International Conference on Computer-Aided Design, 503-508, 2007 | 134 | 2007 |
| TACO: Temperature aware clock-tree optimization M Cho, S Ahmedtt, DZ Pan ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 105 | 2005 |
| Wire density driven global routing for CMP variation and timing M Cho, DZ Pan, H Xiang, R Puri Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 92 | 2006 |
| Double patterning technology friendly detailed routing M Cho, Y Ban, DZ Pan 2008 IEEE/ACM International Conference on Computer-Aided Design, 506-511, 2008 | 89 | 2008 |
| Relative ordering circuit synthesis M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler US Patent 8,756,541, 2014 | 83 | 2014 |
| A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography JS Yang, K Lu, M Cho, K Yuan, DZ Pan 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 637-644, 2010 | 79 | 2010 |
| Powerai ddl M Cho, U Finkler, S Kumar, D Kung, V Saxena, D Sreedhar arXiv preprint arXiv:1708.02188, 2017 | 72 | 2017 |
| MEC: memory-efficient convolution for deep neural network M Cho, D Brand International Conference on Machine Learning, 815-824, 2017 | 66 | 2017 |
| BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability M Cho, K Lu, K Yuan, DZ Pan ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 59 | 2009 |
| Optimal layout decomposition for double patterning technology X Tang, M Cho 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 9-13, 2011 | 51 | 2011 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 49 | 2012 |
| PARADIS: an efficient parallel algorithm for in-place radix sort M Cho, D Brand, R Bordawekar, U Finkler, V Kulandaisamy, R Puri Proceedings of the VLDB Endowment 8 (12), 1518-1529, 2015 | 39 | 2015 |
| ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction M Cho, K Yuan, Y Ban, DZ Pan 2008 45th ACM/IEEE Design Automation Conference, 504-509, 2008 | 37 | 2008 |
| History-based VLSI legalization using network flow M Cho, H Ren, H Xiang, R Puri Proceedings of the 47th Design Automation Conference, 286-291, 2010 | 35 | 2010 |
| BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy M Cho, U Finkler, M Serrano, D Kung, H Hunter IBM Journal of Research and Development 63 (6), 1: 1-1: 11, 2019 | 32 | 2019 |
| Dealing with IC manufacturability in extreme scaling (embedded tutorial paper) B Yu, JR Gao, D Ding, Y Ban, J Yang, K Yuan, M Cho, DZ Pan 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 240-242, 2012 | 30 | 2012 |
| Design for manufacturing meets advanced process control: A survey DZ Pan, P Yu, M Cho, A Ramalingam, K Kim, A Rajaram, SX Shi Journal of Process Control 18 (10), 975-984, 2008 | 30 | 2008 |
| PEAKASO: peak-temperature aware scan-vector optimization M Cho, DZ Pan 24th IEEE VLSI Test Symposium, 6 pp.-57, 2006 | 30 | 2006 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at Austinece.utexas.edu üzerinde doğrulanmış e-posta adresine sahip
