Dae Hyun Kim
Dae Hyun Kim
eecs.wsu.edu üzerinde doğrulanmış e-posta adresine sahip
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
Study of through-silicon-via impact on the 3-D stacked IC layout
DH Kim, K Athikulwongse, SK Lim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (5), 862-874, 2012
3042012
A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout
DH Kim, K Athikulwongse, SK Lim
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 674-680, 2009
3042009
3D-MAPS: 3D Massively parallel processor with stacked memory
DH Kim, K Athikulwongse, M Healy, M Hossain, M Jung, I Khorosh, ...
IEEE International Solid-State Circuits Conference, 188-190, 2012
2042012
Fast and accurate analytical modeling of through-silicon-via capacitive coupling
DH Kim, S Mukhopadhyay, SK Lim
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2011
942011
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
MB Healy, K Athikulwongse, R Goel, MM Hossain, DH Kim, YJ Lee, ...
IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010
932010
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
DH Kim, S Mukhopadhyay, SK Lim
Proceedings of the 11th international workshop on System level interconnect …, 2009
882009
Architectural support for mitigating row hammering in DRAM memories
DH Kim, PJ Nair, MK Qureshi
IEEE Computer Architecture Letters 14 (1), 9-12, 2014
832014
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system
M Cho, C Liu, DH Kim, SK Lim, S Mukhopadhyay
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 694-697, 2010
752010
TSV-aware interconnect length and power prediction for 3D stacked ICs
DH Kim, S Mukhopadhyay, SK Lim
2009 IEEE International Interconnect Technology Conference, 26-28, 2009
692009
Pre-bond and post-bond test and signal recovery structure to characterize and repair TSV defect induced signal degradation in 3-D system
M Cho, C Liu, DH Kim, SK Lim, S Mukhopadhyay
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 …, 2011
642011
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
DH Kim, SK Lim
Proceedings of the 12th ACM/IEEE international workshop on System level …, 2010
642010
Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)
DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ...
IEEE Transactions on Computers 64 (1), 112-125, 2013
622013
Optimizing 3D NoC design for energy efficiency: A machine learning approach
S Das, JR Doppa, DH Kim, PP Pande, K Chakrabarty
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 705-712, 2015
442015
Block-level 3D IC design with through-silicon-via planning
DH Kim, RO Topaloglu, SK Lim
17th Asia and South Pacific Design Automation Conference, 335-340, 2012
362012
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs
T Song, C Liu, DH Kim, SK Lim, J Cho, J Kim, JS Pak, S Ahn, J Kim, ...
2011 12th International Symposium on Quality Electronic Design, 1-7, 2011
362011
TSV-aware interconnect distribution models for prediction of delay and power consumption of 3-D stacked ICs
DH Kim, S Mukhopadhyay, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
322014
Backend low-k TDDB chip reliability simulator
M Bashir, DH Kim, K Athikulwongse, SK Lim, L Milor
2011 International Reliability Physics Symposium, 2C. 2.1-2C. 2.10, 2011
322011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM with 2.5 ns bank to bank active time and no bank group restriction
TY Oh, YS Sohn, SJ Bae, MS Park, JH Lim, YK Cho, DH Kim, DM Kim, ...
IEEE journal of solid-state circuits 46 (1), 107-118, 2010
292010
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown
M Bashir, L Milor, DH Kim, SK Lim
Microelectronics Reliability 50 (9-11), 1341-1346, 2010
262010
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs
DH Kim, S Kim, SK Lim
International Workshop on System Level Interconnect Prediction, 1-8, 2011
242011
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Makaleler 1–20