| Timed pattern matching D Ulus, T Ferrère, E Asarin, O Maler International Conference on Formal Modeling and Analysis of Timed Systems …, 2014 | 53 | 2014 |
| First-order temporal logic monitoring with BDDs K Havelund, D Peled, D Ulus Formal Methods in System Design 56 (1), 1-21, 2020 | 41 | 2020 |
| Online timed pattern matching using derivatives D Ulus, T Ferrère, E Asarin, O Maler International Conference on Tools and Algorithms for the Construction and …, 2016 | 40 | 2016 |
| Montre: A Tool for Monitoring Timed Regular Expressions D Ulus International Conference on Computer Aided Verification, 329-335, 2017 | 32 | 2017 |
| AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic D Ničković, O Lebeltel, O Maler, T Ferrère, D Ulus International Journal on Software Tools for Technology Transfer 22 (6), 741-758, 2020 | 24 | 2020 |
| Measuring with timed patterns T Ferrere, O Maler, D Ničković, D Ulus International Conference on Computer Aided Verification, 322-337, 2015 | 22 | 2015 |
| On the quantitative semantics of regular expressions over real-valued signals A Bakhirkin, T Ferrère, O Maler, D Ulus International Conference on Formal Modeling and Analysis of Timed Systems …, 2017 | 19 | 2017 |
| First-order Temporal Logic Monitoring with BDDs, FMCAD’17 K Havelund, D Peled, D Ulus IEEE, 2017 | 8 | 2017 |
| Derivatives of quantitative regular expressions R Alur, K Mamouras, D Ulus Models, algorithms, logics and tools, 75-95, 2017 | 8 | 2017 |
| Using haloes in mixed-signal assertion based verification D Ulus, A Sen 2012 IEEE International High Level Design Validation and Test Workshop …, 2012 | 6 | 2012 |
| Special session: Embedded software for robotics: Challenges and future directions H Abbas, I Saha, Y Shoukry, R Ehlers, G Fainekos, R Gupta, R Majumdar, ... 2018 International Conference on Embedded Software (EMSOFT), 1-10, 2018 | 5 | 2018 |
| Sequential circuits from regular expressions revisited D Ulus arXiv preprint arXiv:1801.08979, 2018 | 5 | 2018 |
| Online monitoring of metric temporal logic using sequential networks D Ulus arXiv preprint arXiv:1901.00175, 2019 | 4 | 2019 |
| Specifying timed patterns using temporal logic D Ulus, O Maler Proceedings of the 21st International Conference on Hybrid Systems …, 2018 | 4 | 2018 |
| DejaVu: a monitoring tool for first-order temporal logic K Havelund, D Peled, D Ulus 2018 IEEE Workshop on Monitoring and Testing of Cyber-Physical Systems (MT …, 2018 | 4 | 2018 |
| Combining the temporal and epistemic dimensions for MTL monitoring E Asarin, O Maler, D Nickovic, D Ulus International Conference on Formal Modeling and Analysis of Timed Systems …, 2017 | 4 | 2017 |
| Timescales: a benchmark generator for MTL monitoring tools D Ulus International Conference on Runtime Verification, 402-412, 2019 | 3 | 2019 |
| Embedded software for robotics: Challenges and future directions: Special session H Abbas, I Saha, Y Shoukry, R Ehlers, G Fainekos, R Gupta, R Majumdar, ... Proceedings of the International Conference on Embedded Software, 1-10, 2018 | 2 | 2018 |
| Reactive Control Meets Runtime Verification: A Case Study of Navigation D Ulus, C Belta International Conference on Runtime Verification, 368-374, 2019 | 1 | 2019 |
| Pattern Matching with Time: Theory and Applications D Ulus Universite Grenoble-Alpes (UGA), 2018 | 1 | 2018 |
