Krishna T. Malladi
Krishna T. Malladi
System architect, Samsung R&D
Verified email at alumni.stanford.edu - Homepage
Title
Cited by
Cited by
Year
Towards energy-proportional datacenter memory with mobile DRAM
KT Malladi, FA Nothaft, K Periyathambi, BC Lee, C Kozyrakis, M Horowitz
2012 39th Annual International Symposium on Computer Architecture (ISCA), 37-48, 2012
3062012
Drisa: A dram-based reconfigurable in-situ accelerator
S Li, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017
1642017
LazyPIM: An efficient cache coherence mechanism for processing-in-memory
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, K Hsieh, KT Malladi, ...
IEEE Computer Architecture Letters 16 (1), 46-50, 2016
1272016
Rethinking DRAM power modes for energy proportionality
KT Malladi, I Shaeffer, L Gopalakrishnan, D Lo, BC Lee, M Horowitz
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 131-142, 2012
782012
Conda: Efficient cache coherence support for near-data accelerators
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, R Ausavarungnirun, ...
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
332019
Scope: A stochastic computing engine for dram-based in-situ accelerator
S Li, AO Glova, X Hu, P Gu, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
302018
DRAF: A low-power DRAM-based reconfigurable acceleration fabric
M Gao, C Delimitrou, D Niu, KT Malladi, H Zheng, B Brennan, C Kozyrakis
ACM SIGARCH Computer Architecture News 44 (3), 506-518, 2016
262016
DPU architecture
S Li, D Niu, K Malladi, H Zheng
US Patent 10,242,728, 2019
202019
Performance analysis of containerized applications on local and remote storage
Q Xu, M Awasthi, KT Malladi, J Bhimani, J Yang, M Annavaram
Proc. of MSST 3, 24-28, 2017
202017
Reconfigurable logic architecture
M Gao, H Zheng, KT Malladi, R Brennan
US Patent 9,577,644, 2017
192017
Electronic system with partitioning mechanism and method of operation thereof
D Niu, H Zheng, K Malladi
US Patent 9,727,239, 2017
162017
LazyPIM: Efficient support for cache coherence in processing-in-memory architectures
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, N Hajinazar, ...
arXiv preprint arXiv:1706.03162, 2017
132017
Multi-tier buffer management and storage system design for non-volatile memory
J Arulraj, A Pavlo, KT Malladi
arXiv preprint arXiv:1901.10938, 2019
112019
Docker characterization on high performance SSDs
Q Xu, M Awasthi, KT Malladi, J Bhimani, J Yang, M Annavaram
2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017
112017
FlexDrive: A framework to explore NVMe storage solutions
KT Malladi, M Awasthi, H Zheng
2016 IEEE 18th International Conference on High Performance Computing and …, 2016
112016
Rack-level scheduling for reducing the long tail latency using high performance SSDS
Q Xu, K Malladi, M Awasthi
US Patent 10,628,233, 2020
82020
Memory apparatus for in-chip error correction
KT Malladi, H Zheng
US Patent 10,379,939, 2019
82019
CoNDA: Enabling efficient near-data accelerator communication by optimizing data movement
A Boroumand, S Ghose, M Patel, R Ausavarungnirun, H Hassan, B Lucia, ...
ISCA, 2019
52019
Electronic system with memory management mechanism and method of operation thereof
KT Malladi, H Zheng
US Patent 10,073,790, 2018
52018
Space-multiplexing DRAM-based reconfigurable logic
M Gao, H Zheng, KT Malladi
US Patent 9,503,095, 2016
52016
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