| 2018 IEEE Int. Electron Devices Meeting (IEDM) Z Wang, B Crafton, J Gomez, R Xu, A Luo, Z Krivokapic, L Martin, S Datta, ... IEEE 13, 1, 2018 | 343 | 2018 |
| Methods of forming graphene liners and/or cap layers on copper-based conductive structures ET Ryan, Z Krivokapic, X Zhang, C Witt, M He, L Zhao US Patent App. 13/684,871, 2014 | 297 | 2014 |
| Narrow fin finfet Z Krivokapic, JX An, S Dakshina-Murthy, HH Wang, B Yu US Patent 6,921,963, 2005 | 287 | 2005 |
| Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers Z Krivokapic, WD Heavlin, DF Kyser US Patent 5,655,110, 1997 | 265 | 1997 |
| 14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications Z Krivokapic, U Rana, R Galatage, A Razavieh, A Aziz, J Liu, J Shi, ... 2017 IEEE International Electron Devices Meeting (IEDM), 15.1. 1-15.1. 4, 2017 | 245 | 2017 |
| Self-aligned double gate silicon-on-insulator (SOI) device Z Krivokapic, M Buynoski US Patent 6,396,108, 2002 | 189 | 2002 |
| High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: Experiments T Krishnamohan, Z Krivokapic, K Uchida, Y Nishi, KC Saraswat IEEE Transactions on Electron Devices 53 (5), 990-999, 2006 | 168 | 2006 |
| Semiconductor device having a U-shaped gate structure B Yu, SS Ahmed, JX An, S Dakshina-Murthy, Z Krivokapic, HH Wang US Patent 6,833,588, 2004 | 155 | 2004 |
| Shallow trench isolation (STI) region with high-K liner and method of formation OB Karlsson, HH Wang, B Yu, Z Krivokapic, Q Xiang US Patent 6,657,276, 2003 | 132 | 2003 |
| Strained channel finfet S Dakshina-Murthy, JX An, Z Krivokapic, HH Wang, B Yu US Patent 6,803,631, 2004 | 129 | 2004 |
| Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers Z Krivokapic, WD Heavlin, DF Kyser US Patent 5,646,870, 1997 | 121 | 1997 |
| Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates WP Maszara, Z Krivokapic, P King, JS Goo, MR Lin Digest. International Electron Devices Meeting,, 367-370, 2002 | 116 | 2002 |
| Method of forming finned semiconductor devices with trench isolation MR Lin, Z Krivokapic, W Maszara US Patent 7,994,020, 2011 | 113 | 2011 |
| Method for increasing gate capacitance by using both high and low dielectric gate material Z Krivokapic, S Krishnan, GCF Yeap, M Buynoski US Patent 6,087,208, 2000 | 113 | 2000 |
| Method of making a self-aligned triple gate silicon-on-insulator device Z Krivokapic, M Buynoski US Patent 6,716,684, 2004 | 107 | 2004 |
| SOI device with metal source/drain and method of fabrication Z Krivokapic, Q Xiang, B Yu US Patent 6,555,879, 2003 | 107 | 2003 |
| MOSFETs with differing gate dielectrics and method of formation B Yu, Q Xiang, O Karlsson, HH Wang, Z Krivokapic US Patent 6,528,858, 2003 | 103 | 2003 |
| Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication Z Krivokapic US Patent 6,452,229, 2002 | 101 | 2002 |
| FinFET-based SRAM cell Z Krivokapic, JX An, MS Buynoski US Patent 6,765,303, 2004 | 99 | 2004 |
| Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same W Zheng, MW Randolph, NH Tripsas, Z Krivokapic, JF Thomas, ... US Patent 6,861,307, 2005 | 98 | 2005 |
