Arun Kanuparthi
Arun Kanuparthi
Intel Corp. üzerinde doğrulanmış e-posta adresine sahip
Alıntı yapanlar
Alıntı yapanlar
Hardware and embedded security in the context of internet of things
A Kanuparthi, R Karri, S Addepalli
Proceedings of the 2013 ACM workshop on Security, privacy & dependability …, 2013
MAGIC: Malicious Aging in Circuits/Cores
N Karimi, A Kanuparthi, X Wang, R Karri, O Sinanoglu
Transactions on Architecture and Code Optimization, 2015
Securing processors against insider attacks: A circuit-microarchitecture co-design approach
J Rajendran, AK Kanuparthi, M Zahran, SK Addepalli, G Ormazabal, ...
IEEE Design & Test 30 (2), 35-44, 2013
Architecture support for dynamic integrity checking
AK Kanuparthi, M Zahran, R Karri
IEEE Transactions on information forensics and security 7 (1), 321-332, 2011
Hardfails: Insights into software-exploitable hardware bugs
G Dessouky, D Gens, P Haney, G Persyn, A Kanuparthi, H Khattri, ...
28th {USENIX} Security Symposium ({USENIX} Security 19), 213-230, 2019
Feasibility study of dynamic trusted platform module
AK Kanuparthi, M Zahran, R Karri
2010 IEEE International Conference on Computer Design, 350-355, 2010
A high-performance, low-overhead microarchitecture for secure program execution
AK Kanuparthi, R Karri, G Ormazabal, SK Addepalli
2012 IEEE 30th International Conference on Computer Design (ICCD), 102-107, 2012
Techniques for Preventing Memory Timing Attacks
A Kanuparthi, N Kodalapura
US Patent 10,116,436, 2018
Did we learn from LLC Side Channel Attacks? A Cache Leakage Detection Tool for Crypto Libraries
G Irazoqui, K Cong, X Guo, H Khattri, A Kanuparthi, T Eisenbarth, B Sunar
ArXiv, 2017
Controlling Your Control Flow Graph
A Kanuparthi, J Rajendran, R Karri
Hardware Oriented Security and Trust, 6, 2016
A survey of microarchitecture support for embedded processor security
AK Kanuparthi, R Karri, G Ormazabal, SK Addepalli
2012 IEEE Computer Society Annual Symposium on VLSI, 368-373, 2012
Reliable Integrity Checking in Multicore Processors
A Kanuparthi, R Karri
ACM Transactions on Architecture and Code Optimization (TACO), 23, 2015
Formal verification of security critical hardware-firmware interactions in commercial SoCs
S Ray, N Ghosh, RJ Masti, A Kanuparthi, JM Fung
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-4, 2019
When a patch is not enough-hardfails: Software-exploitable hardware bugs
G Dessouky, D Gens, P Haney, G Persyn, A Kanuparthi, H Khattri, ...
arXiv preprint arXiv:1812.00197, 2018
RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities
X Meng, S Kundu, AK Kanuparthi, K Basu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
A Case for Establishing A Common Weakness Enumeration For Hardware Security
JM Fung, A Kanuparthi, H Khattri
(IN)SECURE Magazine, 4-6, 2020
Techniques for preventing memory timing attacks
NN Kodalapura, A Kanuparthi
US Patent App. 16/173,041, 2019
Hardware based technique to prevent critical fine-grained cache side-channel attacks
A Basak, A Kanuparthi, NN Kodalapura, JM Fung
US Patent App. 16/024,072, 2019
Security Assurance in SoCs
A Kanuparthi, H Khattri
IEEE International Conference on Computer Design, 2016
Microarchitecture Support for Security and Reliability
A Kanuparthi
New York University, 2014
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Makaleler 1–20