Swaroop Ghosh
TitleCited byYear
Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era
S Ghosh, K Roy
Proceedings of the IEEE 98 (10), 1718-1751, 2010
1882010
CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation
S Ghosh, S Bhunia, K Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
131*2007
Low-power Variation-tolerant Design in Nanometer Silicon
S Bhunia
Springer Verlag, 2010
662010
Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking
S Ghosh, D Mohapatra, G Karakonstantis, K Roy
IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009
552009
Emerging trends in design and applications of memory-based computing and content-addressable memories
R Karam, R Puri, S Ghosh, S Bhunia
Proceedings of the IEEE 103 (8), 1311-1330, 2015
542015
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
F Hamzaoglu, U Arslan, N Bisnik, S Ghosh, MB Lal, N Lindert, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
482014
A novel on-chip delay measurement hardware for efficient speed-binning
A Raychowdhury, S Ghosh, K Roy
11th IEEE International On-Line Testing Symposium, 287-292, 2005
452005
How secure are printed circuit boards against trojan attacks?
S Ghosh, A Basak, S Bhunia
IEEE Design & Test 32 (2), 7-16, 2014
42*2014
A novel delay fault testing methodology using low-overhead built-in delay sensor
S Ghosh, S Bhunia, A Raychowdhury, K Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
402006
Self-correcting STTRAM under magnetic field attacks
JW Jang, J Park, S Ghosh, S Bhunia
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
392015
A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
S Ghosh, P Ndai, K Roy
Proceedings of the conference on Design, automation and test in Europe, 366-371, 2008
392008
Impact of process-variations in STTRAM and adaptive boosting for robustness
S Motaman, S Ghosh, N Rathi
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
382015
Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6 V 32nm LP SRAM
Y Wang, E Karl, M Meterelliyoz, F Hamzaoglu, YG Ng, S Ghosh, L Wei, ...
2011 International Electron Devices Meeting, 32.1. 1-32.1. 4, 2011
362011
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
S Ghosh, S Bhunia, K Roy
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
342006
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
S Ghosh, R Kaushik
2008 Asia and South Pacific Design Automation Conference, 635-640, 2008
332008
Modeling and analysis of domain wall dynamics for robust and low-power embedded memory
A Iyengar, S Ghosh
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
312014
DWM-PUF: A low-overhead, memory-based security primitive
A Iyengar, K Ramclam, S Ghosh
2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014
292014
Trifecta: A nonspeculative scheme to exploit common, data-dependent subcritical paths
P Ndai, N Rafique, M Thottethodi, S Ghosh, S Bhunia, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (1), 53-65, 2009
282009
Spintronics and security: Prospects, vulnerabilities, attack models, and preventions
S Ghosh
Proceedings of the IEEE 104 (10), 1864-1893, 2016
262016
Design and analysis of novel SRAM PUFs with embedded latch for robustness
JW Jang, S Ghosh
Sixteenth International Symposium on Quality Electronic Design, 298-302, 2015
242015
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