Sang Phill Park
TitleCited byYear
A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
IJ Chang, JJ Kim, SP Park, K Roy
IEEE Journal of Solid-State Circuits 44 (2), 650-658, 2009
4962009
A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS
IJ Chang, JJ Kim, SP Park, K Roy
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical …, 2008
4962008
IMPACT: imprecise adders for low-power approximate computing
V Gupta, D Mohapatra, SP Park, A Raghunathan, K Roy
Low Power Electronics and Design (ISLPED) 2011 International Symposium on …, 2011
3882011
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
K Kang, SP Park, K Roy, MA Alam
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided …, 2007
1102007
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
K Kang, S Gangwal, SP Park, K Roy
Proceedings of the 2008 Asia and South Pacific Design Automation Conference …, 2008
942008
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture
SP Park, S Gupta, N Mojumder, A Raghunathan, K Roy
Proceedings of the 49th Annual Design Automation Conference, 492-497, 2012
932012
Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation
IJ Chang, SP Park, K Roy
IEEE Journal of Solid-State Circuits 45 (2), 401-410, 2010
862010
On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures
K Kang, SP Park, K Kim, K Roy
IEEE transactions on very large scale integration (VLSI) systems 18 (2), 270-280, 2010
812010
Efficient Power Conversion for Ultra Low Voltage Micro Scale Energy Transducers
K Roy, V Raghunathan, C Lu, SP Park, PR Foundation
US Patent US8743574 B2, 2011
752011
Process variation tolerant SRAM array for ultra low voltage applications
JP Kulkarni, K Kim, SP Park, K Roy
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 108-113, 2008
712008
Write-optimized reliable design of STT MRAM
Y Kim, SK Gupta, SP Park, G Panagopoulos, K Roy
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
672012
Layout-aware optimization of STT MRAMs
SK Gupta, SP Park, NN Mojumder, K Roy
Proceedings of the Conference on Design, Automation and Test in Europe, 1455 …, 2012
652012
Efficient power conversion for ultra low voltage micro scale energy transducers
C Lu, SP Park, V Raghunathan, K Roy
Proceedings of the Conference on Design, Automation and Test in Europe, 1602 …, 2010
642010
Reliability implications of bias-temperature instability in digital ICs
SP Park, K Kang, K Roy
Design & Test of Computers, IEEE 26 (6), 8-17, 2009
642009
Spin-transfer torque MRAMs for low power memories: Perspective and prospective
C Augustine, NN Mojumder, X Fong, SH Choday, SP Park, K Roy
IEEE Sensors Journal 12 (4), 756-766, 2011
622011
SHE-NVFF: spin Hall effect-based nonvolatile flip-flop for power gating architecture
KW Kwon, SH Choday, Y Kim, X Fong, SP Park, K Roy
IEEE Electron Device Letters 35 (4), 488-490, 2014
512014
Low-overhead maximum power point tracking for micro-scale solar energy harvesting systems
C Lu, SP Park, V Raghunathan, K Roy
2012 25th International conference on VLSI design, 215-220, 2012
432012
Soft-error-resilient FPGAs using built-in 2-D Hamming product code
SP Park, D Lee, K Roy
IEEE transactions on very large scale integration (VLSI) systems 20 (2), 248-256, 2012
362012
Analysis and design of ultra low power thermoelectric energy harvesting systems
C Lu, SP Park, V Raghunathan, K Roy
Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International …, 2010
332010
Column-selection-enabled 8T SRAM array with∼ 1R/1W multi-port operation for DVFS-enabled processors
SP Park, SY Kim, D Lee, JJ Kim, WP Griffin, K Roy
Low Power Electronics and Design (ISLPED) 2011 International Symposium on …, 2011
212011
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