| FinFET devices with unique fin shape and the fabrication thereof YJ Lee, WU Cheng-Hsien, CH Ko, CH Wann US Patent 9,548,303, 2017 | 933 | 2017 |
| FinFET device having a channel defined in a diamond-like shape semiconductor structure YR Lin, WU Cheng-Hsien, CH Ko, CH Wann US Patent 8,841,701, 2014 | 496 | 2014 |
| Semiconductor structures and methods with high mobility and high energy bandgap materials WU Cheng-Hsien, CH Ko, CH Wann US Patent 8,836,016, 2014 | 419 | 2014 |
| Method for epitaxial re-growth of semiconductor region CT Wan, YR Lin, YJ Lee, WU Cheng-Hsien, CH Ko, CH Wann US Patent 8,815,712, 2014 | 362 | 2014 |
| Contact structure of semiconductor device WU Cheng-Hsien, CH Ko, CH Wann US Patent 8,716,765, 2014 | 353 | 2014 |
| Apparatus and method for FinFETs YJ Lee, YR Lin, CT Wan, WU Cheng-Hsien, CH Ko US Patent 8,742,509, 2014 | 204 | 2014 |
| Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces WU Cheng-Hsien, CH Ko, CH Wann US Patent 8,183,134, 2012 | 180 | 2012 |
| FinFET design and method of fabricating same WU Cheng-Hsien, CH Ko, YT Huang, CH Wann US Patent 8,618,556, 2013 | 179 | 2013 |
| Multiple gate field-effect transistors having oxygen-scavenged gate stack YC Yeo, CC Yeh, CH Ko, WU Cheng-Hsien, LY Chen, XF Yu, YM Chen, ... US Patent 9,564,489, 2017 | 171 | 2017 |
| FinFETs with strained well regions YJ Lee, CW Liu, WU Cheng-Hsien, CH Ko, CH Wann US Patent 9,601,342, 2017 | 155 | 2017 |
| FinFETs with strained well regions YJ Lee, CW Liu, WU Cheng-Hsien, CH Ko, CH Wann US Patent 9,859,380, 2018 | 133 | 2018 |
| FinFETs with strained well regions YJ Lee, CW Liu, WU Cheng-Hsien, CH Ko, CH Wann US Patent 9,159,824, 2015 | 55 | 2015 |
| Source/drain profile for FinFET TC Ma, WU Cheng-Hsien, CH Ko, CH Wann US Patent 9,105,654, 2015 | 51 | 2015 |
| Fabrication, characterization, and analysis of Ge/GeSn heterojunction p-type tunnel transistors C Schulte-Braucks, R Pandey, RN Sajjad, M Barth, RK Ghosh, B Grisafe, ... IEEE Transactions on Electron Devices 64 (10), 4354-4362, 2017 | 38 | 2017 |
| Semiconductor device and manufacturing method thereof IS Chen, WU Cheng-Hsien, CC Yeh US Patent 9,583,399, 2017 | 37 | 2017 |
| FinFET having superlattice stressor YJ Lee, YR Lin, CT Wan, WU Cheng-Hsien, CH Ko US Patent 8,994,002, 2015 | 36 | 2015 |
| Performance benchmarking of p-type In0.65Ga0.35As/GaAs0.4Sb0.6 and Ge/Ge0.93Sn0.07 hetero-junction tunnel FETs R Pandey, C Schulte-Braucks, RN Sajjad, M Barth, RK Ghosh, B Grisafe, ... 2016 IEEE International Electron Devices Meeting (IEDM), 19.6. 1-19.6. 4, 2016 | 32 | 2016 |
| Method of forming CMOS FinFET device WU Cheng-Hsien, CH Ko, CH Wann US Patent 8,486,770, 2013 | 32 | 2013 |
| Multi-gate device and method of fabrication thereof IS Chen, CC Yeh, WU Cheng-Hsien, YC Yeo US Patent 9,660,033, 2017 | 31 | 2017 |
| CMOS devices with reduced leakage and methods of forming the same YJ Lee, WU Cheng-Hsien, CH Ko, CH Wann US Patent 9,224,734, 2015 | 23 | 2015 |
Xinyu BaoTSMCVerified email at tsmc.com
