Santanu Mahapatra
Title
Cited by
Cited by
Year
Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design
S Mahapatra, V Vaish, C Wasshuber, K Banerjee, AM Ionescu
IEEE Transactions on Electron Devices 51 (11), 1772-1782, 2004
1722004
Drive current boosting of n-type tunnel FET with strained SiGe layer at source
N Patel, A Ramesha, S Mahapatra
Microelectronics Journal 39 (12), 1671-1677, 2008
992008
Realization of multiple valued logic and memory by hybrid SETMOS architecture
S Mahapatra, AM Ionescu
IEEE transactions on Nanotechnology 4 (6), 705-714, 2005
962005
Hybrid CMOS single-electron-transistor device and circuit design
S Mahapatra, AM Ionescu
Artech House, Inc., 2006
852006
Monolayer transition metal dichalcogenide channel-based tunnel transistor
RK Ghosh, S Mahapatra
IEEE Journal of the electron devices society 1 (10), 175-180, 2013
832013
A quasi-analytical SET model for few electron circuit simulation
S Mahapatra, AM Ionescu, K Banerjee
IEEE Electron device letters 23 (6), 366-368, 2002
832002
Few electron devices: towards hybrid CMOS-SET integrated circuits
AM Ionescu, MJ Declercq, S Mahapatra, K Banerjee, J Gautier
Proceedings of the 39th annual Design Automation Conference, 88-93, 2002
692002
Modeling of channel potential and subthreshold slope of symmetric double-gate transistor
B Ray, S Mahapatra
IEEE Transactions on Electron Devices 56 (2), 260-266, 2009
602009
Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive
AM Ionescu, S Mahapatra, V Pott
IEEE Electron Device Letters 25 (6), 411-413, 2004
562004
Modelling and analysis of power dissipation in single electron logic
S Mahapatra, AM Ionescu, K Banerjee, MJ Declercq
Digest. International Electron Devices Meeting,, 323-326, 2002
482002
A computationally efficient generalized Poisson solution for independent double-gate transistors
A Sahoo, PK Thakur, S Mahapatra
IEEE transactions on electron devices 57 (3), 632-636, 2010
442010
Modeling and analysis of body potential of cylindrical gate-all-around nanowire transistor
B Ray, S Mahapatra
IEEE transactions on electron devices 55 (9), 2409-2416, 2008
382008
A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits
S Mahapatra, K Banerjee, F Pegeon, AM Ionescu
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
382003
Performance Analysis of Strained Monolayer MoS₂ MOSFET
A Sengupta, RK Ghosh, S Mahapatra
IEEE Transactions on Electron Devices 60 (9), 2782-2787, 2013
302013
Germanane: A low effective mass and high bandgap 2-D channel material for future FETs
RK Ghosh, M Brahma, S Mahapatra
IEEE Transactions on Electron Devices 61 (7), 2309-2315, 2014
292014
SETMOS: A novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs
S Mahapatra, V Pott, S Ecoffey, A Schmid, C Wasshuber, JW Tringe, ...
IEEE International Electron Devices Meeting 2003, 29.7. 1-29.7. 4, 2003
282003
Direct Band-to-Band Tunneling in Reverse Biased MoS₂ nanoribbon p-n junctions
RK Ghosh, S Mahapatra
IEEE Transactions on Electron Devices 60 (1), 274-279, 2013
27*2013
Quantum threshold voltage modeling of short channel quad gate silicon nanowire transistor
PR Kumar, S Mahapatra
IEEE Transactions on Nanotechnology 10 (1), 121-128, 2009
262009
First principles study of metal contacts to monolayer black phosphorous
A Chanana, S Mahapatra
Journal of Applied Physics 116 (20), 204302, 2014
252014
Atomistic modeling of the metallic-to-semiconducting phase boundaries in monolayer MoS2
D Saha, S Mahapatra
Applied Physics Letters 108 (25), 253106, 2016
232016
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