A highly integrated low-power 2.4 GHz transceiver using a direct-conversion diversity receiver in 0.18 µm CMOS for IEEE802. 15.4 WPAN G Retz, H Shanan, K Mulvaney, S O'Mahony, M Chanca, P Crowley, ...
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
88 2009 Frequency tuning for LC circuits H Shanan
US Patent 8,918,070, 2014
61 2014 A 2.4 GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18 µm CMOS for WPAN H Shanan, G Retz, K Mulvaney, P Quinlan
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
38 2009 Calibration system and method for phase-locked loops H Shanan
US Patent 8,049,540, 2011
23 2011 DC-offset-correction system and method for communication receivers H Shanan
US Patent 8,666,343, 2014
20 2014 A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators HN Shanan, MP Kennedy
Proceedings of the 30th European Solid-State Circuits Conference, 123-126, 2004
18 2004 Apparatus and methods for phase-locked loops with temperature compensated calibration voltage H Shanan, MF Keaveney
US Patent 9,413,366, 2016
17 2016 Low noise oscillator having switching network H Shanan
US Patent 8,963,648, 2015
17 2015 Radio transceivers for wireless personal area networks using IEEE802. 15.4 G Retz, H Shanan, K Mulvaney, S O'Mahony, M Chanca, P Crowley, ...
IEEE Communications Magazine 47 (9), 150-158, 2009
17 2009 Image rejection calibration system P Quinlan, M Chanca, H Shanan, V Foley
US Patent 8,358,993, 2013
16 2013 Quality factor tuning for LC circuits H Shanan
US Patent 8,766,712, 2014
15 2014 Oscillator with primary and secondary LC circuits H Shanan
US Patent 9,214,895, 2015
12 2015 Calibration for phase-locked loop H Shanan
US Patent 8,188,778, 2012
11 2012 Phase lock loop RF modulator system CE O'sullivan, C Lyden, HN Shanan
US Patent 7,420,433, 2008
11 2008 A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter,-120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5 ns and 2μs Chirp Settling Time H Shanan, D Dalton, V Chillara, P Dato
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 146-148, 2022
10 2022 A 32–42-GHz RTWO-based frequency quadrupler achieving> 37 dBc harmonic rejection in 22-nm FD-SOI MA Shehata, V Roy, J Breslin, H Shanan, M Keaveney, RB Staszewski
IEEE Solid-State Circuits Letters 4, 72-75, 2021
10 2021 Low-power frequency dividers H Shanan
US Patent 8,294,493, 2012
10 2012 0.3–4.3 GHz Frequency-Accurate Fractional- Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital - Modulator-Based Divider Controller MP Kennedy, H Mo, B Fitzgibbon, A Harney, H Shanan, M Keaveney
IEEE Journal of Solid-State Circuits 49 (7), 1595-1605, 2014
9 2014 Apparatus and methods for rotary traveling wave oscillators H Shanan
US Patent 10,312,922, 2019
6 2019 Apparatus and methods for frequency tuning of rotary traveling wave oscillators H Shanan
US Patent 10,277,233, 2019
6 2019