Gönenç Berkol
Gönenç Berkol
Analog Mixed Signal IC Design Engineer, Analog Devices
analog.com üzerinde doğrulanmış e-posta adresine sahip
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
Adaptive sized quasi-Monte Carlo based yield aware analog circuit optimization tool
E Afacan, G Berkol, AE Pusane, G Dündar, F Başkaya
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
202014
A novel yield aware multi-objective analog circuit optimization tool
G Berkol, E Afacan, G Dündar, AE Pusane, F Başkaya
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2652-2655, 2015
142015
A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena
E Afacan, G Berkol, G Dündar, AE Pusane, F Başkaya
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
132015
A two-step layout-in-the-loop design automation tool
G Berkol, A Unutulmaz, E Afacan, G Dündar, FV Fernandez, AE Pusane, ...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
132015
A hybrid quasi monte carlo method for yield aware analog circuit sizing tool
E Afacan, G Berkol, AE Pusane, G Dündar, F Başkaya
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
132015
Sensitivity based methodologies for process variation aware analog IC optimization
E Afacan, G Berkol, F Başkaya, G Dündar
2014 10th Conference on Ph. D. Research in Microelectronics and Electronics …, 2014
112014
A lifetime-aware analog circuit sizing tool
E Afacan, G Berkol, G Dundar, AE Pusane, F Baskaya
Integration 55, 349-356, 2016
102016
An analog circuit synthesis tool based on efficient and reliable yield estimation
E Afacan, G Berkol, G Dundar, AE Pusane, F Baskaya
Microelectronics Journal 54, 14-22, 2016
102016
Exploring the unknown through successive generations of low power and low resource versatile agents
M Andraud, G Berkol, J De Roose, S Gannavarapu, H Xin, E Cantatore, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
72017
A− 81.6 dBm sensitivity ultrasound transceiver in 65nm CMOS for symmetrical data-links
G Berkol, PGM Baltus, PJA Harpe, E Cantatore
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
32019
Design of a low-power ultrasound transceiver for underwater sensor networks
G Berkol, PGM Baltus, PJA Harpe, E Cantatore
2018 14th Conference on Ph. D. Research in Microelectronics and Electronics …, 2018
32018
A 2.67 μJ per measurement FMCW ultrasound rangefinder system for the exploration of enclosed environments
G Berkol, PGM Baltus, PJA Harpe, E Cantatore
IEEE Solid-State Circuits Letters 3, 326-329, 2020
22020
A hierarchical design automation concept for analog circuits
G Berkol, E Afacan, G Dündar, EV Fernandez
2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016
22016
A 1.25 μJ per Measurement Ultrasound Rangefinder System in 65 nm CMOS for Explorations With a Swarm of Sensor Nodes
G Berkol, PGM Baltus, PJA Harpe, E Cantatore
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (4), 1409-1420, 2021
12021
An analog behavioral equivalence boundary search methodology for simulink models and circuit level designs utilizing evolutionary computation
MO Saglamdemir, G Berkol, G Dundar, A Sen
Integration 55, 366-375, 2016
12016
Architecture and IC Implementation of Ultrasound Communication and Rangefinder Systems for Sensor Swarms
G Berkol
2021
Post-silicon validation of yield-aware analog circuit synthesis
E Afacan, G Berkol, G Dündar
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
2019
2020 Index IEEE Solid-State Circuits Letters Vol. 3
L Aschei, G Ascheid, M Asghari, M Asker, S Asuncion, G Atzeni, M Auer, ...
SMACD 2019, Lausanne, Switzerland
R Abd-Alhameed, A Abdulkhaleq, H Aboushady, E Afacan, S Ahmed, ...
PRIME 2018, Prague, Czech Republic
A Agambayev, R Ahamed, T Al-Attar, N Alam, S Allani, A Almansouri, ...
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Makaleler 1–20