| ScaffCC: a framework for compilation and analysis of quantum computing programs A JavadiAbhari, S Patil, D Kudrow, J Heckey, A Lvov, FT Chong, ... Proceedings of the 11th ACM Conference on Computing Frontiers, 1, 2014 | 187 | 2014 |
| ScaffCC: Scalable compilation and analysis of quantum programs A JavadiAbhari, S Patil, D Kudrow, J Heckey, A Lvov, FT Chong, ... Parallel Computing 45, 2-17, 2015 | 169 | 2015 |
| Implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages DV Rao, S Patil, NA Babu, V Muthukumar International Journal of Theoretical and Applied Computer Sciences 1 (1), 9-34, 2006 | 120 | 2006 |
| Direct communication between magnetic tunnel junctions for nonvolatile logic fan-out architecture A Lyle, J Harms, S Patil, X Yao, DJ Lilja, JP Wang Applied Physics Letters 97 (15), 152504, 2010 | 85 | 2010 |
| MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computing M Imani, S Patil, TS Rosing Proceedings of the 2016 Conference on Design, Automation & Test in Europe …, 2016 | 70 | 2016 |
| Approximate computing using multiple-access single-charge associative memory M Imani, S Patil, T Rosing IEEE Transactions on Emerging Topics in Computing, 2016 | 68 | 2016 |
| Compiler management of communication and parallelism for quantum computation J Heckey, S Patil, A JavadiAbhari, A Holmes, D Kudrow, KR Brown, ... ACM SIGARCH Computer Architecture News 43 (1), 445-456, 2015 | 59 | 2015 |
| Low power data-aware STT-RAM based hybrid cache architecture M Imani, S Patil, T Rosing Quality Electronic Design (ISQED), 2016 17th International Symposium on, 88-94, 2016 | 55 | 2016 |
| Magnetic tunnel junction logic architecture for realization of simultaneous computation and communication A Lyle, S Patil, J Harms, B Glass, X Yao, D Lilja, JP Wang IEEE Transactions on Magnetics 47 (10), 2970-2973, 2011 | 43 | 2011 |
| Spintronic logic gates for spintronic data using magnetic tunnel junctions S Patil, A Lyle, J Harms, DJ Lilja, JP Wang Computer Design (ICCD), 2010 IEEE International Conference on, 125-131, 2010 | 41 | 2010 |
| CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile Devices Y Kim, M Imani, S Patil, TS Rosing Proceedings of the IEEE/ACM International Conference on Computer-Aided …, 2015 | 33 | 2015 |
| Using resampling techniques to compute confidence intervals for the harmonic mean of rate-based performance metrics S Patil, DJ Lilja IEEE Computer Architecture Letters 9 (1), 1-4, 2010 | 25 | 2010 |
| Hierarchical design of robust and low data dependent FinFET based SRAM array M Imani, S Patil, TS Rosing Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on …, 2015 | 21 | 2015 |
| Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions SR Patil, X Yao, H Meng, JP Wang, DJ Lilja Proceedings of the 5th conference on Computing frontiers, 171-178, 2008 | 18 | 2008 |
| A pure single-walled carbon nanotube thin film based three-terminal microelectromechanical switch MW Jang, CL Chen, WE Partlo III, SR Patil, D Lee, Z Ye, D Lilja, TA Taton, ... Applied Physics Letters 98 (7), 073502, 2011 | 16 | 2011 |
| Characterization of User’s Behavior Variations for Design of Replayable Mobile Workloads S Patil, Y Kim, K Korgaonkar, I Awwal, TS Rosing International Conference on Mobile Computing, Applications, and Services, 51-70, 2015 | 14 | 2015 |
| Statistical methods for computer performance evaluation S Patil, DJ Lilja Wiley Interdisciplinary Reviews: Computational Statistics 4 (1), 98-106, 2012 | 9 | 2012 |
| Characterizing the performance effect of trials and rotations in applications that use Quantum Phase Estimation S Patil, A JavadiAbhari, CF Chiang, J Heckey, M Martonosi, FT Chong Workload Characterization (IISWC), 2014 IEEE International Symposium on, 181-190, 2014 | 8 | 2014 |
| Systems and methods for direct communication between magnetic tunnel junctions DJ Lilja, JP Wang, AP Lyle, SR Patil, JD Harms, X Yao US Patent 20120314489A1, 2012 | 8 | 2012 |
| DCC: Double Capacity Cache Architecture for Narrow-Width Values M Imani, S Patil, T Rosing Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 113-116, 2016 | 7 | 2016 |
