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Marie-Lise Flottes
Marie-Lise Flottes
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Title
Cited by
Cited by
Year
A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans
S Dupuis, PS Ba, G Di Natale, ML Flottes, B Rouzeyre
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 49-54, 2014
2732014
Scan Design and Secure Chip.
D Hély, ML Flottes, F Bancel, B Rouzeyre, N Berard, M Renovell
IOLTS 4, 219-224, 2004
2012004
Test control for secure scan designs
D Hely, F Bancel, ML Flottes, B Rouzeyre
European Test Symposium (ETS'05), 190-195, 2005
1202005
Test versus security: Past and present
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
IEEE Transactions on Emerging topics in Computing 2 (1), 50-62, 2014
1122014
New security threats against chips containing scan chain structures
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2011 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2011
832011
Are advanced DfT structures sufficient for preventing scan-attacks?
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2012 IEEE 30th VLSI Test Symposium (VTS), 246-251, 2012
822012
A novel differential scan attack on advanced DFT structures
JD Rolt, GD Natale, ML Flottes, B Rouzeyre
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013
712013
Scan attacks and countermeasures in presence of scan response compactors
J DaRolt, G Di Natale, ML Flottes, B Rouzeyre
2011 Sixteenth IEEE European Test Symposium, 19-24, 2011
652011
Preventing scan attacks on secure circuits through scan chain encryption
M Da Silva, ML Flottes, G Di Natale, B Rouzeyre
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
592018
Logic locking: A survey of proposed methods and evaluation metrics
S Dupuis, ML Flottes
Journal of Electronic Testing 35, 273-291, 2019
572019
Secure scan techniques: a comparison
D Hely, F Bancel, ML Flottes, B Rouzeyre
12th IEEE International On-Line Testing Symposium (IOLTS'06), 6 pp., 2006
562006
A reliable architecture for parallel implementations of the advanced encryption standard
G Di Natale, M Doulcier, ML Flottes, B Rouzeyre
Journal of Electronic Testing 25 (4), 269-278, 2009
542009
Securing scan control in crypto chips
D Hély, F Bancel, ML Flottes, B Rouzeyre
Journal of Electronic Testing 23 (5), 457-464, 2007
542007
Secure JTAG implementation using Schnorr protocol
A Das, J Da Rolt, S Ghosh, S Seys, S Dupuis, G Di Natale, ML Flottes, ...
Journal of Electronic Testing 29, 193-209, 2013
532013
Self-test techniques for crypto-devices
G Di Natale, M Doulcier, ML Flottes, B Rouzeyre
IEEE transactions on very large scale integration (VLSI) systems 18 (2), 329-333, 2009
512009
Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model
JM Dutertre, V Beroulle, P Candelier, S De Castro, LB Faber, ML Flottes, ...
2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 1-6, 2018
492018
Protection against hardware trojans with logic testing: Proposed solutions and challenges ahead
S Dupuis, ML Flottes, G Di Natale, B Rouzeyre
IEEE Design & Test 35 (2), 73-90, 2017
482017
Analyzing testability from behavioral to RT level
ML Flottes, R Pires, B Rouzeyre
Proceedings European Design and Test Conference. ED & TC 97, 158-165, 1997
431997
A new scan attack on rsa in presence of industrial countermeasures
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
Constructive Side-Channel Analysis and Secure Design: Third International …, 2012
402012
New testing procedure for finding insertion sites of stealthy hardware Trojans
S Dupuis, PS Ba, ML Flottes, G Di Natale, B Rouzeyre
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 776-781, 2015
392015
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