| Current mirror array: A novel circuit topology for combining physical unclonable function and machine learning Z Wang, Y Chen, A Patil, J Jayabalan, X Zhang, CH Chang, A Basu IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1314-1326, 2017 | 54 | 2017 |
| Active through-silicon interposer based 2.5 D IC design, fabrication, assembly and test J Jayabalan, V Chidambaram, SLP Siang, W Xiangyu, JM Chinq, ... 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 587-593, 2019 | 15 | 2019 |
| Compliant probes and test methodology for fine pitch wafer level devices and interconnects J Jayabalan, M Rotaru, M Iyer, A Ong US Patent App. 11/207,336, 2007 | 15 | 2007 |
| Integration of SRAM redundancy into production test J Jayabalan, J Povazanec Proceedings. International Test Conference, 187-193, 2002 | 13 | 2002 |
| Test strategies for fine pitch wafer level packaged devices J Jayabalan, MD Rotaru, D Chun, FH Hua, MK Iyer, BL Ooi, MS Leong, ... Proceedings of the 5th Electronics Packaging Technology Conference (EPTC …, 2003 | 6 | 2003 |
| A scaling technique for partial element equivalent circuit analysis using SPICE J Jayabalan, OB Leong, LM Seng, MK Iyer IEEE microwave and wireless components letters 14 (5), 216-218, 2004 | 5 | 2004 |
| Multi-gigahertz Testing of wafer-level packaged devices AM Majid, DC Keezer, J Jayabalan, MR Rotaru 2006 IEEE International Test Conference, 1-10, 2006 | 4 | 2006 |
| Wafer level reliability characterization of 2.5 D IC packages J Jayabalan, JM Chinq, V Chidambaram, SLP Siang, CCH Ming, ... 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), 274-277, 2018 | 3 | 2018 |
| Novel circuit model for three-dimensional geometries with multilayer dielectrics J Jayabalan, BL Ooi, MS Leong, MK Iyer IEEE transactions on microwave theory and techniques 54 (4), 1331-1339, 2006 | 2 | 2006 |
| PEEC model for multiconductor systems including dielectric mesh J Jayabalan, BL Ooi, A Irene, MS Leong, MK Iyer 2005 Asia-Pacific Microwave Conference Proceedings 2, 3 pp., 2005 | 2 | 2005 |
| A methodology for accurate modeling of a pad structure from S‐parameter measurements J Jayabalan, BL Ooi, B Wu, DS Xu, MK Iyer, MS Leong Microwave and Optical Technology Letters 45 (2), 115-118, 2005 | 2 | 2005 |
| Test bench modeling and characterization for fine pitch wafer level packaged devices J Jayabalan, RD Mihai, JPH Tan, MK Iyer, OB Leong, LM Seng Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004 …, 2004 | 2 | 2004 |
| Signal Delay Based Temperature Determination for Production Testing of Advanced Packages J Jayabalan, S Ahmad, N Khan 2008 10th Electronics Packaging Technology Conference, 144-148, 2008 | | 2008 |
| A novel test strategy for fine pitch wafer-level packaged devices J Jayabalan, MD Rotaru, VS Rao, V Kripesh, MK Iyer, AAO Tay, BL Ooi, ... IEEE transactions on advanced packaging 30 (3), 439-447, 2007 | | 2007 |
| Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package J JAYABALAN | | 2006 |
| Modelling and application of elastomer mesh for microwave probing J Jayabalan, BL Ooi, MS Leong, MK Iyer IEE Proceedings-Microwaves, Antennas and Propagation 153 (1), 83-88, 2006 | | 2006 |
| Circuit model of elastomer probe for fine pitch wafer level package test applications J Jayabalan, BL Ooi, MS Leong, MK Iyer 2005 7th Electronic Packaging Technology Conference 1, 4 pp., 2005 | | 2005 |
| High frequency characterization of 100 micron pitch wafer level package interconnects J Jayabalan, MD Rotaru 2005 7th Electronic Packaging Technology Conference 1, 4 pp., 2005 | | 2005 |
| Energetics of Copper Nanowires J Jayabalan, R Jayaganthan, AAO Tay, OB Leong International Journal of Nanoscience 4 (04), 717-723, 2005 | | 2005 |
| PLL based high speed functional testing JJ etal Asian Test Symposium, 2003 | | 2003 |
Mihai RotaruInstitute of MicroelectronicsVerified email at ime.a-star.edu.sg
