cheng liu
Title
Cited by
Cited by
Year
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip
C Liu, L Zhang, Y Han, X Li
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 357-362, 2011
692011
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay
C Liu, HC Ng, HKH So
2015 International Conference on Field Programmable Technology (FPT), 56-63, 2015
362015
NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing
X Yang, Z Qing-li, F Fang-fa, Y Ming-yan, L Cheng
2007 7th International Conference on ASIC, 890-893, 2007
322007
A resilient on-chip router design through data path salvaging
C Liu, L Zhang, Y Han, X Li
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 437-442, 2011
302011
Economizing TSV Resources in 3-D Network-on-Chip Design
Y Wang, YH Han, L Zhang, BZ Fu, C Liu, HW Li, X Li
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-13, 2014
272014
A survey on graph processing accelerators: Challenges and opportunities
CY Gui, L Zheng, B He, C Liu, XY Chen, XF Liao, H Jin
Journal of Computer Science and Technology 34 (2), 339-371, 2019
172019
A soft processor overlay with tightly-coupled FPGA accelerator
HC Ng, C Liu, HKH So
arXiv preprint arXiv:1606.06483, 2016
162016
FPGA overlays
HKH So, C Liu
FPGAs for Software Programmers, 285-305, 2016
152016
Automatic nested loop acceleration on fpgas using soft CGRA overlay
C Liu, HC Ng, HKH So
arXiv preprint arXiv:1509.00042, 2015
152015
FCN-engine: Accelerating deconvolutional layers in classic CNN processors
D Xu, K Tu, Y Wang, C Liu, B He, H Li
Proceedings of the International Conference on Computer-Aided Design, 1-6, 2018
132018
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency
C Liu, CL Yu, HKH So
Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual …, 2013
122013
Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware
X Zhao, Y Wang, X Cai, C Liu, L Zhang
International Conference on Learning Representations (ICLR), 2020
82020
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks
S Liang, Y Wang, C Liu, L He, LI Huawei, D Xu, X Li
IEEE Transactions on Computers, 2020
72020
A virtual channel allocation algorithm for noc
D Bao, X Li, Y Xin, J Yang, X Ren, F Fu, C Liu
International Conference on Machine Learning and Intelligent Communications …, 2017
42017
Squeezing the last MHz for cnn acceleration on FPGAs
L Li, D Xu, K Xing, C Liu, Y Wang, H Li, X Li
2019 IEEE International Test Conference in Asia (ITC-Asia), 151-156, 2019
32019
Resilient neural network training for accelerators with computing errors
D Xu, K Xing, C Liu, Y Wang, Y Dai, L Cheng, H Li, L Zhang
2019 IEEE 30th International Conference on Application-specific Systems …, 2019
32019
RevivePath: Resilient network-on-chip design through data path salvaging of router
YH Han, C Liu, H Lu, WB Li, L Zhang, XW Li
Journal of Computer Science and Technology 28 (6), 1045-1053, 2013
32013
OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs
C Liu, X Chen, B He, X Liao, Y Wang, L Zhang
2019 International Conference on Field-Programmable Technology (ICFPT), 315-318, 2019
22019
Exploring emerging CNFET for efficient last level cache design
D Xu, L Li, Y Wang, C Liu, H Li
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
22019
Training for'Unstable'CNN Accelerator: A Case Study on FPGA
KZ Xing
arXiv preprint arXiv:1812.01689, 2018
22018
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