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Cristiano Lazzari
Cristiano Lazzari
Broadcom
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Design of digit-serial FIR filters: Algorithms, architectures, and a CAD tool
L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro
IEEE transactions on very large Scale integration (VLSI) systems 21 (3), 498-511, 2012
542012
Efficient shift-adds design of digit-serial multiple constant multiplications
L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro
Proceedings of the 21st edition of the great lakes symposium on Great lakes†…, 2011
272011
Asymmetric transistor sizing targeting radiation-hardened circuits
C Lazzari, G Wirth, FL Kastensmidt, L Anghel, RAL Reis
Electrical Engineering 94, 11-18, 2012
262012
A new test scheduling algorithm based on networks-on-chip as test access mechanisms
AM Amory, C Lazzari, MS Lubaszewski, FG Moraes
Journal of Parallel and Distributed Computing 71 (5), 675-686, 2011
222011
Optimization of area in digit-serial multiple constant multiplications at gate-level
L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2737-2740, 2011
212011
CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs
RCG da Silva, C Lazzari, H Boudinov, L Carro
Microelectronics Journal 40 (10), 1466-1470, 2009
192009
A new transistor-level layout generation strategy for static CMOS circuits
C Lazzari, C Santos, R Reis
2006 13th IEEE International Conference on Electronics, Circuits and Systems†…, 2006
192006
A new quaternary FPGA based on a voltage-mode multi-valued circuit
C Lazzari, P Flores, J Monteiro, L Carro
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010†…, 2010
182010
A transistor sizing method applied to an automatic layout generation tool
C Santos, G Wilke, C Lazzari, R Reis, JL Guntzel
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003†…, 2003
152003
An efficient low power multiple-value look-up table targeting quaternary FPGAs
C Lazzari, J Fernandes, P Flores, J Monteiro
Integrated Circuit and System Design. Power and Timing Modeling†…, 2011
142011
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies.
C Lazzari, CV Domingues, JLA GŁntzel, RA da Luz Reis
VLSI-SOC, 193-197, 2003
122003
An automated design methodology for layout generation targeting power leakage minimization
C Lazzari, A Ziesemer, R Reis
2009 16th IEEE International Conference on Electronics, Circuits and Systems†…, 2009
102009
Power and delay comparison of binary and quaternary arithmetic circuits
C Lazzari, P Flores, JC Monteiro
2009 3rd International Conference on Signals, Circuits and Systems (SCS), 1-6, 2009
92009
Radix-2 decimation in time (DIT) FFT implementation based on a matrix-multiple constant multiplication approach
S Ghissoni, E Costa, C Lazzari, J Monteiro, L Aksoy, R Reis
2010 17th IEEE International Conference on Electronics, Circuits and Systems†…, 2010
82010
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications
L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro
Integration 45 (3), 294-306, 2012
72012
A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs
M Ritt, CAL Lisboa, L Carro, C Lazzari
2010 International Conference on Field Programmable Logic and Applications†…, 2010
72010
Transistor level automatic generation of radiation-hardened circuits
C Lazzari
Institut National Polytechnique de Grenoble-INPG, 2007
72007
Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies.
L Anghel, C Lazzari, M Nicolaidis
LATW, 186-191, 2006
72006
SET fault injection methods in analog circuits: Case study
A Ammari, L Anghel, R Leveugle, C Lazzari, R Reis
TIMA, http://tima. imag. fr/alfa-nicron/documents/8set_fault. pdf, 2007
62007
On implementing a soft error hardening technique by using an automatic layout generator: case study
C Lazzari, L Anghel, RAL Reis
11th IEEE International On-Line Testing Symposium, 29-34, 2005
62005
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Articles 1–20