Vivek Joy Kozhikkottu
Vivek Joy Kozhikkottu
Research Scientist, Intel Corp
Verified email at intel.com
Title
Cited by
Cited by
Year
SALSA: systematic logic synthesis of approximate circuits
S Venkataramani, A Sabne, V Kozhikkottu, K Roy, A Raghunathan
DAC Design Automation Conference 2012, 796-801, 2012
2902012
TapeCache: a high density, energy efficient cache based on domain wall memory
R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ...
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
1202012
Structures of vertical resistors and FETs as controlled by electrical field penetration and a band-gap voltage reference using vertical FETs operating in accumulation through …
M Chi
US Patent App. 10/268,585, 2004
562004
Cache design with domain wall memory
R Venkatesan, VJ Kozhikkottu, M Sharad, C Augustine, A Raychowdhury, ...
IEEE Transactions on Computers 65 (4), 1010-1024, 2015
202015
Variation aware cache partitioning for multithreaded programs
V Kozhikkottu, A Pan, V Pai, S Dey, A Raghunathan
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
92014
VESPA: Variability emulation for System-on-Chip performance analysis
VJ Kozhikkottu, R Venkatesan, A Raghunathan, S Dey
2011 Design, Automation & Test in Europe, 1-6, 2011
92011
Recovery-based design for variation-tolerant SoCs
V Kozhikkottu, S Dey, A Raghunathan
DAC Design Automation Conference 2012, 826-833, 2012
82012
Increasing read pending queue capacity to increase memory bandwidth
G Koo, V Kozhikkottu, SG Ramasubramanian, CB Wilkerson
US Patent App. 15/395,615, 2018
22018
Energy efficient read/write support for a protected memory
V Kozhikkottu, D Somasekhar, YM Kim, SP Park
US Patent App. 15/089,340, 2017
22017
Techniques for setting a 2-level auto-close timer to access a memory device
V Kozhikkottu, S Chittor, E Choukse, SG Ramasubramanian
US Patent App. 16/584,612, 2020
12020
Low latency statistical data bus inversion for energy reduction
V Kozhikkottu, SG Ramasubramanian, KW Kwon, D Somasekhar
US Patent App. 15/475,571, 2018
12018
Variation tolerant design of a vector processor for recognition, mining and synthesis
V Kozhikkottu, S Venkataramani, S Dey, A Raghunathan
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
12014
Integrated multi-purpose wireless network transceiver
CY Huang
US Patent App. 10/319,461, 2004
12004
Address range based in-band memory error-correcting code protection module with syndrome buffer
AA Radjai, N Aboulenein, SL Geiger, SA Jadhav, BJ Kapadia, ...
US Patent App. 16/504,199, 2019
2019
Memory device with local cache array
JW Lee, V Kozhikkottu, KS Bains, H Alameer
US Patent App. 16/433,663, 2019
2019
Error correction code (ecc) and data bus inversion (dbi) encoding
VJ Kozhikkottu, SG Ramasubramanian, D Somasekhar, M Dadual
US Patent App. 16/420,504, 2019
2019
Logic Synthesis of Approximate Circuits
S Venkataramani, V Kozhikkottu, A Sabne, K Roy, A Raghunathan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019
2019
Low-overhead mechanism to detect address faults in ECC-protected memories
KW Kwon, V Kozhikkottu, D Somasekhar
US Patent 10,319,461, 2019
2019
Fast search of error correction code (ecc) protected data in a memory
W Wu, D Somasekhar, J Stephan, AK Radhakrishnan, V Kozhikkottu
US Patent App. 16/249,631, 2019
2019
Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data
KW Kwon, V Kozhikkottu, SP Park, A More, WP Griffin, R Pawlowski, ...
US Patent App. 15/477,072, 2018
2018
The system can't perform the operation now. Try again later.
Articles 1–20