| AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement I Alouani, WM Elsharkasy, AM Eltawil, FJ Kurdahi, S Niar IET Circuits, Devices & Systems 11 (1), 89-94, 2017 | 27 | 2017 |
| NUVA: architectural support for runtime verification of parametric specifications over multicores A Nassar, FJ Kurdahi, W Elsharkasy Proceedings of the 2015 International Conference on Compilers, Architecture …, 2015 | 20 | 2015 |
| Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches WM Elsharkasy, A Khajeh, AM Eltawil, FJ Kurdahi IEEE Transactions on Circuits and Systems I: Regular Papers, 2017 | 13 | 2017 |
| Efficient pulsed-latch implementation for multiport register files: work-in-progress WM Elsharkasy, HE Yantir, A Khajeh, AM Eltawil, FJ Kurdahi Proceedings of the 2017 International Conference on Compilers, Architectures …, 2017 | 2* | 2017 |
| Low overhead correction scheme for unreliable LDPC buffering AM Hussien, WM Elsharkasy, AM Eltawil, F Kurdahi, A Khajeh Global Conference on Signal and Information Processing (GlobalSIP), 2013 …, 2013 | 2 | 2013 |
| FPGA implementation of high speed XTS-AES for data storage devices M Elmoghany, M Diab, M Kassem, M Khairallah, O El Shahat, W Sharkasy Internet Technology and Secured Transactions (ICITST), 2011 International …, 2011 | 2 | 2011 |
| Low Power Reliable Design using Pulsed Latch Circuits WM Elsharkasy | 1 | 2017 |
| Hardware modelling of JPEG2000 MQ-encoder WM El-Sharkasy, ME Ragab Intelligent and Advanced Systems (ICIAS), 2012 4th International Conference …, 2012 | 1 | 2012 |
| Runtime Verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification methods. To address the substantial … A Nassar, FJ Kurdahi, W Elsharkasy | | |
