Jae-Joon Kim
Jae-Joon Kim
Verified email at postech.ac.kr - Homepage
Title
Cited by
Cited by
Year
A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
IJ Chang, JJ Kim, SP Park, K Roy
IEEE Journal of Solid-State Circuits 44 (2), 650-658, 2009
5062009
Sense-amp based adder with source follower evaluation tree
JJ Kim, CTK Chuang, RV Joshi, K Roy
US Patent 6,789,099, 2004
2152004
Double gate-MOSFET subthreshold circuit for ultralow power applications
JJ Kim, K Roy
IEEE Transactions on Electron Devices 51 (9), 1468-1474, 2004
1442004
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
CH Kim, JJ Kim, S Mukhopadhyay, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (3), 349-357, 2005
1262005
Back-gate controlled read SRAM cell
JJ Kim, K Kim
US Patent 7,177,177, 2007
1042007
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang
Microelectronics reliability 49 (6), 642-649, 2009
942009
A forward body-biased low-leakage SRAM cache: device and architecture considerations
CH Kim, JJ Kim, S Mukhopadhyay, K Roy
Proceedings of the 2003 international symposium on Low power electronics and …, 2003
722003
SRAM write-ability improvement with transient negative bit-line voltage
S Mukhopadhyay, RM Rao, JJ Kim, CT Chuang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (1), 24-32, 2009
672009
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
CT Chuang, S Mukhopadhyay, JJ Kim, K Kim, R Rao
2007 IEEE International Workshop on Memory Technology, Design and Testing, 4-12, 2007
652007
PVT-aware leakage reduction for on-die caches with improved read stability
CH Kim, JJ Kim, IJ Chang, K Roy
IEEE Journal of Solid-State Circuits 41 (1), 170-178, 2005
562005
Robust level converter for sub-threshold/super-threshold operation: 100 mV to 2.5 v
IJ Chang, J Kim, K Kim, K Roy
IEEE transactions on very large scale integration (VLSI) systems 19 (8 …, 2010
432010
Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance
A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang
2009 IEEE International Reliability Physics Symposium, 745-749, 2009
432009
A completely digital on-chip circuit for local-random-variability measurement
R Rao, KA Jenkins, JJ Kim
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
412008
Asymmetrical SRAM cells with enhanced read and write margins
K Kim, JJ Kim, CT Chuang
2007 International Symposium on VLSI Technology, Systems and Applications …, 2007
372007
Asymmetrical memory cells and memories using the cells
CT Chuang, JJ Kim, K Kim
US Patent 7,362,606, 2008
352008
Robust level converter design for sub-threshold logic
IJ Chang, JJ Kim, K Roy
Proceedings of the 2006 international symposium on Low power electronics and …, 2006
342006
On-chip process variation detection using slew-rate monitoring circuit
A Ghosh, RM Rao, J Kim, CT Chuang, RB Brown
21st International Conference on VLSI Design (VLSID 2008), 143-149, 2008
312008
Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors
JJ Kim, A Bansal, R Rao, SH Lo, CT Chuang
IEEE Electron Device Letters 30 (8), 852-854, 2009
302009
Improved synapse device with MLC and conductance linearity using quantized conduction for neuromorphic systems
S Lim, C Sung, H Kim, T Kim, J Song, JJ Kim, H Hwang
IEEE Electron Device Letters 39 (2), 312-315, 2018
282018
Self‐Assembled, Millimeter‐Sized TIPS‐Pentacene Spherulites Grown on Partially Crosslinked Polymer Gate Dielectric
H Yoo, HH Choi, TJ Shin, T Rim, K Cho, S Jung, JJ Kim
Advanced Functional Materials 25 (24), 3658-3665, 2015
272015
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Articles 1–20