Hai (Helen) Li
Hai (Helen) Li
Clare Boothe Luce Professor of Electrical and Computer Engineering
Verified email at duke.edu - Homepage
Cited by
Cited by
Learning structured sparsity in deep neural networks
W Wen, C Wu, Y Wang, Y Chen, H Li
Advances in neural information processing systems, 2074-2082, 2016
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
X Dong, X Wu, G Sun, Y Xie, H Li, Y Chen
2008 45th ACM/IEEE Design Automation Conference, 554-559, 2008
Spintronic memristor through spin-torque-induced magnetization motion
X Wang, Y Chen, H Xi, H Li, D Dimitrov
IEEE electron device letters 30 (3), 294-297, 2009
Terngrad: Ternary gradients to reduce communication in distributed deep learning
W Wen, C Xu, F Yan, C Wu, Y Wang, Y Chen, H Li
Advances in neural information processing systems, 1509-1519, 2017
Pipelayer: A pipelined reram-based accelerator for deep learning
L Song, X Qian, H Li, Y Chen
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Z Sun, X Bi, H Li, WF Wong, ZL Ong, X Zhu, W Wu
proceedings of the 44th annual IEEE/ACM international symposium on …, 2011
Memristor crossbar-based neuromorphic computing system: A case study
M Hu, H Li, Y Chen, Q Wu, GS Rose, RW Linderman
IEEE transactions on neural networks and learning systems 25 (10), 1864-1878, 2014
DRG-cache: a data retention gated-ground cache for low power
A Agarwal, H Li, K Roy
Proceedings 2002 Design Automation Conference (IEEE Cat. No. 02CH37324), 473-478, 2002
Emerging non-volatile memories: opportunities and challenges
CJ Xue, Y Zhang, Y Chen, G Sun, JJ Yang, H Li
Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011
A single-V/sub t/low-leakage gated-ground cache for deep submicron
A Agarwal, H Li, K Roy
IEEE Journal of Solid-state circuits 38 (2), 319-328, 2003
A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement
G Sun, Y Joo, Y Chen, Y Chen, Y Xie
Emerging Memory Technologies, 51-77, 2014
Hardware realization of BSB recall function using memristor crossbar arrays
M Hu, H Li, Q Wu, GS Rose
DAC Design Automation Conference 2012, 498-503, 2012
Deterministic clock gating for microprocessor power reduction
H Li, S Bhunia, Y Chen, TN Vijaykumar, K Roy
The Ninth International Symposium on High-Performance Computer Architecture …, 2003
Faster cnns with direct sparse convolutions and guided pruning
J Park, S Li, W Wen, PTP Tang, H Li, Y Chen, P Dubey
arXiv preprint arXiv:1608.01409, 2016
Resistive sense memory calibration for self-reference read method
Y Chen, H Li, W Zhu, X Wang, H Huang, H Liu
US Patent 7,898,838, 2011
RENO: A high-efficient reconfigurable neuromorphic computing accelerator design
X Liu, M Mao, B Liu, H Li, Y Chen, B Li, Y Wang, H Jiang, M Barnell, Q Wu, ...
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
Rescuing memristor-based neuromorphic design with high defects
C Liu, M Hu, JP Strachan, H Li
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies
Y Chen, X Wang, H Li, H Xi, Y Yan, W Zhu
IEEE transactions on very large scale integration (VLSI) systems 18 (12 …, 2009
Learning intrinsic sparse structures within long short-term memory
W Wen, Y He, S Rajbhandari, M Zhang, W Wang, F Liu, B Hu, Y Chen, ...
arXiv preprint arXiv:1709.05027, 2017
Cross-layer racetrack memory design for ultra high density and low power consumption
Z Sun, W Wu, H Li
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2013
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