Jim Tschanz
Jim Tschanz
Verified email at intel.com
Title
Cited by
Cited by
Year
Parameter variations and impact on circuits and microarchitecture
S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De
Proceedings of the 40th annual Design Automation Conference, 338-342, 2003
17492003
A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS
R Jain, BM Geuskens, ST Kim, MM Khellah, J Kulkarni, JW Tschanz, V De
IEEE Journal of Solid-State Circuits 49 (4), 917-927, 2014
872014
Variation-tolerant circuits: circuit solutions and techniques
J Tschanz, K Bowman, V De
Proceedings of the 42nd annual Design Automation Conference, 762-763, 2005
832005
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
A Raychowdhury, B Geuskens, J Kulkarni, J Tschanz, K Bowman, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 352-353, 2010
722010
Numerical analysis of domain wall propagation for dense memory arrays
C Augustine, A Raychowdhury, B Behin-Aein, S Srinivasan, J Tschanz, ...
2011 International Electron Devices Meeting, 17.6. 1-17.6. 4, 2011
472011
A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14-nm Tri-gate CMOS
HK Krishnamurthy, V Vaidya, P Kumar, R Jain, S Weng, ST Kim, ...
IEEE Journal of Solid-State Circuits 53 (1), 8-19, 2017
422017
Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays
C Augustine, A Raychowdhury, D Somasekhar, J Tschanz, K Roy, VK De
2010 International Electron Devices Meeting, 22.7. 1-22.7. 4, 2010
412010
Design for resilience to soft errors and variations
M Zhang, TM Mak, J Tschanz, KS Kim, N Seifert, D Lu
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 23-28, 2007
402007
A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS
R Jain, B Geuskens, M Khellah, S Kim, J Kulkarni, J Tschanz, V De
2013 Symposium on VLSI Circuits, C174-C175, 2013
312013
Dual-VCC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range
J Kulkarni, M Khellah, J Tschanz, B Geuskens, R Jain, S Kim, V De
2013 Symposium on VLSI Technology, C126-C127, 2013
272013
A 22nm dynamically adaptive clock distribution for voltage droop tolerance
KA Bowman, C Tokunaga, T Karnik, VK De, JW Tschanz
2012 Symposium on VLSI Circuits (VLSIC), 94-95, 2012
182012
Reliability challenges in nano-CMOS Design
Y Cao, P Bose, J Tschanz
IEEE Design & Test of Computers, 6-7, 2009
132009
Error detection and correction in microprocessor core and memory due to fast dynamic voltage droops
A Raychowdhury, J Tschanz, K Bowman, SL Lu, P Aseron, M Khellah, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (3 …, 2011
122011
A low-power, reconfigurable adaptive equalizer architecture
J Tschanz, NR Shanbhag
Conference Record of the Thirty-Third Asilomar Conference on Signals …, 1999
121999
Characterization of inverse temperature dependence in logic circuits
M Cho, M Khellah, K Chae, K Ahmed, J Tschanz, S Mukhopadhyay
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012
112012
Minimum supply voltage for sequential logic circuits in a 22nm technology
CH Chen, K Bowman, C Augustine, Z Zhang, J Tschanz
International Symposium on Low Power Electronics and Design (ISLPED), 181-186, 2013
102013
Guest editors' introduction: Reliability challenges in nano-cmos design
Y Cao, J Tschanz, P Bose
IEEE Design & Test of Computers 26 (6), 6-7, 2009
102009
Impacts on Circuits and Microarchitecture
S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi
DAC 10, 775832.775920, 2003
42003
Numerical analysis of a novel MTJ stack for high readability and writability
A Raychowdhury, C Augustine, D Somasekhar, J Tschanz, K Roy, V De
2011 Proceedings of the European Solid-State Device Research Conference …, 2011
32011
On-line detection and correction of errors due to fast, dynamic voltage droop events
J Tschanz, K Bowman, S Lu, P Aseron, M Khellah, A Raychowdhury, ...
Proceeding of Silicon Errors in Logic–System Effects, 2010
22010
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